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[X86] Don't reorder (srl (and X, C1), C2) if (and X, C1) can be matched as a movzx
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Authored by craig.topper on Jan 19 2018, 12:47 PM.

Details

Summary

If we can match as a zero extend there's no need to flip the order to get an encoding benefit. As movzx is 3 bytes with independent source/dest registers. The shortest 'and' we could make is also 3 bytes unless we get lucky in the register allocator and its on AL/AX/EAX which have a 2 byte encoding.

This patch was more impressive before r322957 went in. It removed some of the same Ands that got deleted by that patch.

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Repository
rL LLVM

Event Timeline

craig.topper created this revision.Jan 19 2018, 12:47 PM

Rebase after adding zext-demanded.ll test

spatel accepted this revision.Jan 22 2018, 6:57 AM

LGTM.

This revision is now accepted and ready to land.Jan 22 2018, 6:57 AM
This revision was automatically updated to reflect the committed changes.