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Differential D42069

[X86] Add missing predicates for VRNDSCALES{D,S}{m,r}
ClosedPublic

Authored by courbet on Jan 15 2018, 6:20 AM.

Details

Reviewers
gchatelet
Commits
rGda1fad3ec643: [X86] Add missing predicates for VRNDSCALES{D,S}{m,r}
rL322486: [X86] Add missing predicates for VRNDSCALES{D,S}{m,r}
Summary

This is similar to https://reviews.llvm.org/D41983.

Diff Detail

Repository
rL LLVM

Event Timeline

courbet created this revision.Jan 15 2018, 6:20 AM
Harbormaster completed remote builds in B13837: Diff 129851.Jan 15 2018, 6:20 AM
gchatelet accepted this revision.Jan 15 2018, 6:23 AM

LGTM.

This revision is now accepted and ready to land.Jan 15 2018, 6:23 AM
Closed by commit rL322486: [X86] Add missing predicates for VRNDSCALES{D,S}{m,r} (authored by courbet). · Explain WhyJan 15 2018, 6:25 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
2 lines

Diff 129854

llvm/trunk/lib/Target/X86/X86InstrAVX512.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,013 Lines • ▼ Show 20 Linesmulticlass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst), defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.IntScalarMemOp:$src2, i32u8imm:$src3), (ins _.RC:$src1, _.IntScalarMemOp:$src2, i32u8imm:$src3),
OpcodeStr, OpcodeStr,
"$src3, $src2, $src1", "$src1, $src2, $src3", "$src3, $src2, $src1", "$src1, $src2, $src3",
(_.VT (X86RndScales _.RC:$src1, (_.VT (X86RndScales _.RC:$src1,
_.ScalarIntMemCPat:$src2, (i32 imm:$src3))), itins.rm>, _.ScalarIntMemCPat:$src2, (i32 imm:$src3))), itins.rm>,
Sched<[itins.Sched.Folded, ReadAfterLd]>; Sched<[itins.Sched.Folded, ReadAfterLd]>;
let isCodeGenOnly = 1, hasSideEffects = 0 in { let isCodeGenOnly = 1, hasSideEffects = 0, Predicates = [HasAVX512] in {
def r : I<opc, MRMSrcReg, (outs _.FRC:$dst), def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
(ins _.FRC:$src1, _.FRC:$src2, i32u8imm:$src3), (ins _.FRC:$src1, _.FRC:$src2, i32u8imm:$src3),
OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
[], itins.rr>, Sched<[itins.Sched]>; [], itins.rr>, Sched<[itins.Sched]>;
let mayLoad = 1 in let mayLoad = 1 in
def m : I<opc, MRMSrcMem, (outs _.FRC:$dst), def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
(ins _.FRC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3), (ins _.FRC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
▲ Show 20 Lines • Show All 2,680 Lines • Show Last 20 Lines