[CodeGen] Move printing MO_Immediate operands to MachineOperand::print

[thegameg]

Summary

Work towards the unification of MIR and debug output by refactoring the interfaces.

Add support for operand subreg index as an immediate to debug printing and use ::print in the MIRPrinter.

No tests were affected as all the %subreg. tests were all checking MIR output.

[thegameg]

Make MIRLangRef more clear about subreg index immediate operands.

[MatzeB]

include/llvm/CodeGen/MachineOperand.h

248–259

Would it make sense to move the subreg index printing into its own function instead of a toggle flag? As in that case most of the other arguments won't be used.

lib/CodeGen/MachineInstr.cpp

1262–1266

This case must be a register def I think, so it cannot be a subregidx operand.

1295–1299

An ASM also wouldn't have subregidx operands.

1345–1348

DBG_VALUEs also don't have subregidx operands.

[MatzeB]

LGTM

lib/CodeGen/MIRPrinter.cpp

857–868

I guess this could be:

case MachineOperand::MO_Immediate:
  if (MI.isOperandSubregIdx(OpIdx)) {
    printSubReg();
    break;
   }
   LLVM_FALLTHROUGH;
case MachineOperand::MO_Register:
   //...

[thegameg]

Committed as r320209: [CodeGen] Move printing MO_Immediate operands to MachineOperand::print (failed the commit message...)

docs/MIRLangRef.rst

 The immediate machine operands are untyped, 64-bit signed integers. The
 example below shows an instance of the X86 ``MOV32ri`` instruction that has an
 immediate machine operand ``-42``:
 
 .. code-block:: text
 
     %eax = MOV32ri -42
 
+An immediate operand is also used to represent a subregister index when the
+machine instruction has one of the following opcodes:
+
+- ``EXTRACT_SUBREG``
+
+- ``INSERT_SUBREG``
+
+- ``REG_SEQUENCE``
+
+- ``SUBREG_TO_REG``
+
+In case this is true, the Machine Operand is printed according to the target.
+
+For example:
+
+In AArch64RegisterInfo.td:
+
+.. code-block:: text
+
+  def sub_32 : SubRegIndex<32>;
+
+If the third operand is an immediate with the value ``15`` (target-dependent
+value), based on the instruction's opcode and the operand's index the operand
+will be printed as ``%subreg.sub_32``:
+
+.. code-block:: text
+
+    %1:gpr64 = SUBREG_TO_REG 0, %0, %subreg.sub_32
+
 .. TODO: Describe the CIMM (Rare) and FPIMM immediate operands.
 
 .. _register-operands:
 
 Register Operands
 ^^^^^^^^^^^^^^^^^
 
 The :ref:`register <registers>` primitive is used to represent the register

include/llvm/CodeGen/MachineOperand.h

public:
   /// \param PrintDef - whether we want to print `def` on an operand which
   /// isDef. Sometimes, if the operand is printed before '=', we don't print
   /// `def`.
   /// \param ShouldPrintRegisterTies - whether we want to print register ties.
   /// Sometimes they are easily determined by the instruction's descriptor
   /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
   /// \param TiedOperandIdx - if we need to print register ties this needs to
   /// provide the index of the tied register. If not, it will be ignored.
+  /// \param IsOperandSubregIdx - MO_Immediate operands can also be subreg
+  /// idices. If it's the case, the subreg index name will be printed.
+  /// MachineInstr::isOperandSubregIdx can be called to check this.
   /// \param TRI - provide more target-specific information to the printer.
   /// Unlike the previous function, this one will not try and get the
   /// information from it's parent.
   /// \param IntrinsicInfo - same as \p TRI.
   void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
              bool PrintDef, bool ShouldPrintRegisterTies,
-             unsigned TiedOperandIdx, const TargetRegisterInfo *TRI,
+             unsigned TiedOperandIdx, bool IsOperandSubregIdx,
+             const TargetRegisterInfo *TRI,
              const TargetIntrinsicInfo *IntrinsicInfo) const;
 
   void dump() const;
 
   //===--------------------------------------------------------------------===//
   // Accessors that tell you what kind of MachineOperand you're looking at.
   //===--------------------------------------------------------------------===//
 
   /// isReg - Tests if this is a MO_Register operand.

lib/CodeGen/MIRPrinter.cpp

 
 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
                       const TargetRegisterInfo *TRI,
                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
                       bool PrintDef) {
   const MachineOperand &Op = MI.getOperand(OpIdx);
   printTargetFlags(Op);
   switch (Op.getType()) {
-  case MachineOperand::MO_Register: {
+  case MachineOperand::MO_Register:
+  case MachineOperand::MO_Immediate: {
     unsigned TiedOperandIdx = 0;
-    if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
+    if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
+    bool IsOperandSubregIdx = Op.isImm() && MI.isOperandSubregIdx(OpIdx);
     Op.print(OS, MST, TypeToPrint, PrintDef, ShouldPrintRegisterTies,
-             TiedOperandIdx, TRI, TII);
+             TiedOperandIdx, IsOperandSubregIdx, TRI, TII);
     break;
   }
-  case MachineOperand::MO_Immediate:
-    if (MI.isOperandSubregIdx(OpIdx))
-      OS << "%subreg." << TRI->getSubRegIndexName(Op.getImm());
-    else
-      OS << Op.getImm();
-    break;
   case MachineOperand::MO_CImmediate:
     Op.getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
     break;
   case MachineOperand::MO_FPImmediate:
     Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
     break;
   case MachineOperand::MO_MachineBasicBlock:
     OS << printMBBReference(*Op.getMBB());
     break;

lib/CodeGen/MachineInstr.cpp

void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
   unsigned StartOp = 0, e = getNumOperands();
   for (; StartOp < e && getOperand(StartOp).isReg() &&
          getOperand(StartOp).isDef() && !getOperand(StartOp).isImplicit();
        ++StartOp) {
     if (StartOp != 0)
       OS << ", ";
     LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
     unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
+    bool IsOperandSubregIdx =
+        getOperand(StartOp).isImm() && isOperandSubregIdx(StartOp);
     getOperand(StartOp).print(OS, MST, TypeToPrint, /*PrintDef=*/false,
-                              ShouldPrintRegisterTies, TiedOperandIdx, TRI,
-                              IntrinsicInfo);
+                              ShouldPrintRegisterTies, TiedOperandIdx,
+                              IsOperandSubregIdx, TRI, IntrinsicInfo);
     unsigned Reg = getOperand(StartOp).getReg();
     if (TargetRegisterInfo::isVirtualRegister(Reg))
       VirtRegs.push_back(Reg);
   }
 
   if (StartOp != 0)
     OS << " = ";
 
void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
   unsigned AsmOpCount = 0;
 
   if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
     // Print asm string.
     OS << " ";
     const unsigned OpIdx = InlineAsm::MIOp_AsmString;
     LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
     unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
+    bool IsOperandSubregIdx =
+        getOperand(OpIdx).isImm() && isOperandSubregIdx(OpIdx);
     getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true,
-                            ShouldPrintRegisterTies, TiedOperandIdx, TRI,
-                            IntrinsicInfo);
+                            ShouldPrintRegisterTies, TiedOperandIdx,
+                            IsOperandSubregIdx, TRI, IntrinsicInfo);
 
     // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
     unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
     if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
       OS << " [sideeffect]";
     if (ExtraInfo & InlineAsm::Extra_MayLoad)
       OS << " [mayload]";
     if (ExtraInfo & InlineAsm::Extra_MayStore)
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
     if (isDebugValue() && MO.isMetadata()) {
       // Pretty print DBG_VALUE instructions.
       auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
       if (DIV && !DIV->getName().empty())
         OS << "!\"" << DIV->getName() << '\"';
       else {
         LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
         unsigned TiedOperandIdx = getTiedOperandIdx(i);
+        bool IsOperandSubregIdx = MO.isImm() && isOperandSubregIdx(i);
         MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true,
-                 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
+                 ShouldPrintRegisterTies, TiedOperandIdx, IsOperandSubregIdx,
+                 TRI, IntrinsicInfo);
       }
     } else if (TRI && (isInsertSubreg() || isRegSequence() ||
                        (isSubregToReg() && i == 3)) && MO.isImm()) {
       OS << TRI->getSubRegIndexName(MO.getImm());
     } else if (i == AsmDescOp && MO.isImm()) {
       // Pretty print the inline asm operand descriptor.
       OS << '$' << AsmOpCount++;
       unsigned Flag = MO.getImm();
if (isDebugValue() && MO.isMetadata()) {
 
       OS << ']';
 
       // Compute the index of the next operand descriptor.
       AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
     } else {
       LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
       unsigned TiedOperandIdx = getTiedOperandIdx(i);
+      bool IsOperandSubregIdx = MO.isImm() && isOperandSubregIdx(i);
       MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, ShouldPrintRegisterTies,
-               TiedOperandIdx, TRI, IntrinsicInfo);
+               TiedOperandIdx, IsOperandSubregIdx, TRI, IntrinsicInfo);
     }
   }
 
   bool HaveSemi = false;
   const unsigned PrintableFlags = FrameSetup | FrameDestroy;
   if (Flags & PrintableFlags) {
     if (!HaveSemi) {
       OS << ";";

lib/CodeGen/MachineOperand.cpp

 }
 
 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
                            const TargetIntrinsicInfo *IntrinsicInfo) const {
   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
   ModuleSlotTracker DummyMST(nullptr);
   print(OS, DummyMST, LLT{}, /*PrintDef=*/false,
         /*ShouldPrintRegisterTies=*/true,
-        /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
+        /*TiedOperandIdx=*/0, /*IsOperandSubregIdx=*/false, TRI, IntrinsicInfo);
 }
 
 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
                            LLT TypeToPrint, bool PrintDef,
                            bool ShouldPrintRegisterTies,
                            unsigned TiedOperandIdx,
+                           bool IsOperandSubregIdx,
                            const TargetRegisterInfo *TRI,
                            const TargetIntrinsicInfo *IntrinsicInfo) const {
   switch (getType()) {
   case MachineOperand::MO_Register: {
     unsigned Reg = getReg();
     if (isImplicit())
       OS << (isDef() ? "implicit-def " : "implicit ");
     else if (PrintDef && isDef())
case MachineOperand::MO_Register: {
     if (ShouldPrintRegisterTies && isTied() && !isDef())
       OS << "(tied-def " << TiedOperandIdx << ")";
     // Print types.
     if (TypeToPrint.isValid())
       OS << '(' << TypeToPrint << ')';
     break;
   }
   case MachineOperand::MO_Immediate:
+    if (IsOperandSubregIdx) {
+      OS << "%subreg.";
+      if (TRI)
+        OS << TRI->getSubRegIndexName(getImm());
+      else
+        OS << getImm();
+    } else
       OS << getImm();
     break;
+
   case MachineOperand::MO_CImmediate:
     getCImm()->getValue().print(OS, false);
     break;
   case MachineOperand::MO_FPImmediate:
     if (getFPImm()->getType()->isFloatTy()) {
       OS << getFPImm()->getValueAPF().convertToFloat();
     } else if (getFPImm()->getType()->isHalfTy()) {
       APFloat APF = getFPImm()->getValueAPF();

unittests/CodeGen/MachineOperandTest.cpp

 //===- MachineOperandTest.cpp ---------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/ilist_node.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/IR/ModuleSlotTracker.h"
 #include "llvm/Support/raw_ostream.h"
 #include "gtest/gtest.h"
 
 using namespace llvm;
 
 namespace {
 
 TEST(MachineOperandTest, ChangeToTargetIndexTest) {
TEST(MachineOperandTest, PrintSubReg) {
   // Print a MachineOperand containing a SubReg. Here we check that without a
   // TRI and IntrinsicInfo we can still print the subreg index.
   std::string str;
   raw_string_ostream OS(str);
   MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
   ASSERT_TRUE(OS.str() == "%physreg1.subreg5");
 }
 
+TEST(MachineOperandTest, PrintSubRegIndex) {
+  // Create a MachineOperand with an immediate and print it as a subreg index.
+  MachineOperand MO = MachineOperand::CreateImm(3);
+
+  // Checking some preconditions on the newly created
+  // MachineOperand.
+  ASSERT_TRUE(MO.isImm());
+  ASSERT_TRUE(MO.getImm() == 3);
+
+  // Print a MachineOperand containing a SubRegIdx. Here we check that without a
+  // TRI and IntrinsicInfo we can print the operand as a subreg index.
+  std::string str;
+  raw_string_ostream OS(str);
+  ModuleSlotTracker DummyMST(nullptr);
+  MO.print(OS, DummyMST, LLT{}, /*PrintDef=*/false,
+           /*ShouldPrintRegisterTies=*/false,
+           /*TiedOperandIdx=*/0, /*IsOperandSubregIdx=*/true, nullptr, nullptr);
+  ASSERT_TRUE(OS.str() == "%subreg.3");
+}
+
 } // end namespace