[PATCH] Fix for http://llvm.org/bugs/show_bug.cgi?id=19905

[sanjoy]

Summary

This patch fixes issue 19905. This solution isn't as clean as I'd
like it to be, but I haven't been able to come up with something that
would be both cleaner and not super invasive.

Another possible fix for this that seems cleaner to me is to have the
x86 spillCalleeSavedRegisters routine emit MOVs and not PUSHes (except
maybe for %rbp, to spare the debugger), with MO_FrameIndex operands.
These MOV instructions could then be peephole-optimized into sequences
of PUSHes and POPs if possible, after the frame indices have been
mapped to actual stack slot offsets. I'm not sure how feasible this
is, though.

[vadimcn]

Hi Sanjay,
Please take a look at my preliminary patch to support Win64 SEH I've put here: http://reviews.llvm.org/D4053 (specifically stuff in X86FrameLowering.cpp). Not directly related to 19905, however, it touches the same code, and could benefit from the same refactoring.

Firstly, I think that spill slots will have to go into fixed frame slots, because in order to describe them in terms of Win64 SEH directives, the spilled XMM registers need to be addressable from the frame pointer. Right now they end up on the wrong side of the "stack realignment gap" in cases when stack is realigned.

Also, as I was working on this code, a couple of questions popped in my mind:

1. Why does PrologueEpilogueInserter pre-assign spill slots to registers before calling spillCalleeSavedRegisters? Wouldn't it be more logical to let spillCalleeSavedRegisters do that (only if it is going to return true, of course).
2. Wouldn't it make sense to move the actual emission of PUSHes and MOVs into emitPrologue? I think this would make CFI/SEH info generation much more straightforward. spillCalleeSavedRegisters would still have to assign the spill slots, of course. The only downside I see, is that this code wouldn't be able to use TII.storeRegToStackSlot(), because by that point frame slots have already been reified.

[vadimcn]

Looking at the llc output you provided in the bug, I notice that it spilled and emitted CFI info for XMM registers. What target was that compiled for? AFAIK, only Windows 64 ABI specifies XMMs as callee-saved. So if it was for Win64, my patch would directly address your problem.

[asl]

test/CodeGen/X86/pr19905.ll

26

You redefined CFA register above to be %rbp. So, not, this is not stack pointer just before the call anymore.

-120 is because the rule here is"take the address from %rbp and add 16 to it". %rbx is 13th register to be pushed, so we have to offset by 13 * -8 - 16 ;)

[sanjoy]

In D4052#5, @vadimcn wrote:

Looking at the llc output you provided in the bug, I notice that it spilled and emitted CFI info for XMM registers. What target was that compiled for? AFAIK, only Windows 64 ABI specifies XMMs as callee-saved. So if it was for Win64, my patch would directly address your problem.

Hi Vadim,

I haven't looked at your change yet, but this change has nothing to do
with Win64 specifically. The test case simply forces llvm (using
llvm.eh.unwind.init) to spill out all the registers as CSRs, and the
.cfi_offset values emitted demonstrate the bug I'm trying to address.

[sanjoy]

In D4052#4, @vadimcn wrote:

Hi Sanjay,
Please take a look at my preliminary patch to support Win64 SEH I've put here: http://reviews.llvm.org/D4053 (specifically stuff in X86FrameLowering.cpp). Not directly related to 19905, however, it touches the same code, and could benefit from the same refactoring.

Yes, I think you could do away with MaxSpillSlotOffset once this
change (or something like this) is in, and just use getObjectOffset.
This is assuming I correctly understand what MaxSpillSlotOffset is
used for. :)

Firstly, I think that spill slots will have to go into fixed frame slots, because in order to describe them in terms of Win64 SEH directives, the spilled XMM registers need to be addressable from the frame pointer. Right now they end up on the wrong side of the "stack realignment gap" in cases when stack is realigned.

I don't know anything about the Win64 ABI, so I won't comment on this.
However, I think the above issue is orthogonal to this change.

Also, as I was working on this code, a couple of questions popped in my mind:

1. Why does PrologueEpilogueInserter pre-assign spill slots to registers before calling spillCalleeSavedRegisters? Wouldn't it be more logical to let spillCalleeSavedRegisters do that (only if it is going to return true, of course).

I think PEI pre-assigns frame indices, not actual spill slots. Also
spillCalleeSavedRegisters is a TargetFrameLowering function, and the
logic to assign frame indices is target agnostic, so maybe that's the
reason for putting it in PEI. A point to note is that this issue
doesn't have any direct relation to eager / early assignment of frame
indices.

2. Wouldn't it make sense to move the actual emission of PUSHes and MOVs into emitPrologue? I think this would make CFI/SEH info generation much more straightforward. spillCalleeSavedRegisters would still have to assign the spill slots, of course. The only downside I see, is that this code wouldn't be able to use TII.storeRegToStackSlot(), because by that point frame slots have already been reified.

At this time I don't have enough insight to comment on the pros and
cons of such a change; especially whether such a change simplifies x86
code at the cost of making other backends more complex.

[vadimcn]

@sanjoy, I wonder what happens with your patch in case of stack re-alignment.
Sorry, I can't figure out how to get git to apply your diff. Could you please try it on the following IR:

declare void @llvm.eh.unwind.init()

define coldcc void @calls_unwind_init() {
  %s = alloca i32, align 64
  call void @llvm.eh.unwind.init()
  ret void
}

If CFI info for XMM registers still correct?

[sanjoy]

test/CodeGen/X86/pr19905.ll

26

Makes sense, I'll fix the comment in the next iteration of the patch. :)

[sanjoy]

In D4052#9, @vadimcn wrote:

@sanjoy, I wonder what happens with your patch in case of stack re-alignment.
Sorry, I can't figure out how to get git to apply your diff. Could you please try it on the following IR:

declare void @llvm.eh.unwind.init()

define coldcc void @calls_unwind_init() {
  %s = alloca i32, align 64
  call void @llvm.eh.unwind.init()
  ret void
}

If CFI info for XMM registers still correct?

Hi Vadim,

With my changes the CFI info for the above snippet isn't correct, for the reason you mentioned earlier -- the xmm registers are spilled *after* the stack realignment, and I don't see how you could even correctly access them using %rbp.

[vadimcn]

I've updated my patch. It should now solve your problem too.

[sanjoy]

The issue has already been fixed on llvm upstream.

include/llvm/Target/TargetFrameLowering.h

   /// the assembly prologue to explicitly handle the stack.
   virtual void adjustForHiPEPrologue(MachineFunction &MF) const { }
 
-  /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
-  /// saved registers and returns true if it isn't possible / profitable to do
-  /// so by issuing a series of store instructions via
-  /// storeRegToStackSlot(). Returns false otherwise.
+  /// spillCalleeSavedRegisters - Issues instruction(s) to spill all
+  /// callee saved registers and returns true if it isn't possible /
+  /// profitable to do so by issuing a series of store instructions
+  /// via storeRegToStackSlot().  Populates CSRSlots with [frame
+  /// index, offset] pairs for the frame indices that had to be
+  /// eagerly assigned stack slots by the instruction spilling code
+  /// (eg. by x86 push instructions).  Returns false otherwise.
   virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MI,
                                         const std::vector<CalleeSavedInfo> &CSI,
+                                         DenseMap<int, int> &CSRSlots,
                                          const TargetRegisterInfo *TRI) const {
     return false;
   }

lib/CodeGen/PrologEpilogInserter.h

     // stack frame indexes.
     unsigned MinCSFrameIndex, MaxCSFrameIndex;
 
+    // CSRSlots - Maps the frame indices that have already beeen
+    // assigned an offset by spillCalleeSavedRegisters to the offset
+    // they have been assigned.  The offset is from the value of the
+    // stack pointer before executing the CSR spilling code.
+    DenseMap<int, int> CSRSlots;
+
     // Entry and return blocks of the current function.
     MachineBasicBlock* EntryBlock;
     SmallVector<MachineBasicBlock*, 4> ReturnBlocks;

lib/CodeGen/PrologEpilogInserter.cpp

   // These are used to keep track the callee-save area. Initialize them.
   MinCSFrameIndex = INT_MAX;
   MaxCSFrameIndex = 0;
+  CSRSlots.clear();
 
   // Early exit for targets which have no callee saved registers.
   if (!CSRegs || CSRegs[0] == 0)

 
   // Spill using target interface.
   I = EntryBlock->begin();
-  if (!TFI->spillCalleeSavedRegisters(*EntryBlock, I, CSI, TRI)) {
+  if (!TFI->spillCalleeSavedRegisters(*EntryBlock, I, CSI, CSRSlots, TRI)) {
     for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
       // Add the callee-saved register as live-in.
       // It's killed at the spill.

     if (FixedOff > Offset) Offset = FixedOff;
   }
 
-  // First assign frame offsets to stack objects that are used to spill
-  // callee saved registers.
+  // Reify the stack offsets that were implicitly assigned to CSR
+  // frame indices.
+  const int CSRSlotsStart = Offset;
+  for (auto I = CSRSlots.begin(), E = CSRSlots.end(); I != E; ++I) {
+    int thisFrameIdx = I->first;
+    int thisOffset = I->second;
+
+    int64_t nextOffset = 0;
+
+    if (StackGrowsDown) {
+      thisOffset = CSRSlotsStart + (-thisOffset);
+      nextOffset = thisOffset;
+      MFI->setObjectOffset(thisFrameIdx, -thisOffset);
+    } else {
+      thisOffset = CSRSlotsStart + thisOffset;
+      nextOffset = thisOffset + MFI->getObjectSize(thisFrameIdx);
+      MFI->setObjectOffset(thisFrameIdx, thisOffset);
+    }
+
+    Offset = std::max(Offset, nextOffset);
+  }
+
+  // Offset now points to the end of the block of offsets implicitly
+  // assigned by the target specific spill code.  Here we deal with
+  // the frame indices left over.
+
   if (StackGrowsDown) {
     for (unsigned i = MinCSFrameIndex; i <= MaxCSFrameIndex; ++i) {
+      if (CSRSlots.count(i)) { continue; }  // already assigned a slot above
+
       // If the stack grows down, we need to add the size to find the lowest
       // address of the object.
       Offset += MFI->getObjectSize(i);

   } else {
     int MaxCSFI = MaxCSFrameIndex, MinCSFI = MinCSFrameIndex;
     for (int i = MaxCSFI; i >= MinCSFI ; --i) {
+      if (CSRSlots.count(i)) { continue; }   // already assigned a slot above
+
       unsigned Align = MFI->getObjectAlignment(i);
       // Adjust to alignment boundary
       Offset = (Offset+Align-1)/Align*Align;

lib/Target/AArch64/AArch64FrameLowering.h

   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
+                                 DenseMap<int, int> &CSRSlots,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,

lib/Target/AArch64/AArch64FrameLowering.cpp

 bool AArch64FrameLowering::spillCalleeSavedRegisters(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
     const std::vector<CalleeSavedInfo> &CSI,
-    const TargetRegisterInfo *TRI) const {
+    DenseMap<int, int> &CSRSlots, const TargetRegisterInfo *TRI) const {
   MachineFunction &MF = *MBB.getParent();
   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
   unsigned Count = CSI.size();

lib/Target/ARM/ARMFrameLowering.h

   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
+                                 DenseMap<int, int> &CSRSlots,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,

lib/Target/ARM/ARMFrameLowering.cpp

 bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         const std::vector<CalleeSavedInfo> &CSI,
+                                        DenseMap<int, int> &CSRSlots,
                                         const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;

lib/Target/ARM/Thumb1FrameLowering.h

   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
+                                 DenseMap<int, int> &CSRSlots,
                                  const TargetRegisterInfo *TRI) const override;
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,

lib/Target/ARM/Thumb1FrameLowering.cpp

 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MI,
                           const std::vector<CalleeSavedInfo> &CSI,
+                          DenseMap<int, int> &CSRSlots,
                           const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;

lib/Target/Hexagon/HexagonFrameLowering.h

   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
+                                 DenseMap<int, int> &CSRSlots,
                                  const TargetRegisterInfo *TRI) const override;
 
   void

lib/Target/Hexagon/HexagonFrameLowering.cpp

                                         MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         const std::vector<CalleeSavedInfo> &CSI,
+                                        DenseMap<int, int> &CSRSlots,
                                         const TargetRegisterInfo *TRI) const {
   MachineFunction *MF = MBB.getParent();
   const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();

lib/Target/MSP430/MSP430FrameLowering.h

   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
+                                 DenseMap<int, int> &CSRSlots,
                                  const TargetRegisterInfo *TRI) const override;
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,

lib/Target/MSP430/MSP430FrameLowering.cpp

 MSP430FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                            MachineBasicBlock::iterator MI,
                                         const std::vector<CalleeSavedInfo> &CSI,
+                                        DenseMap<int, int> &CSRSlots,
                                         const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;

lib/Target/Mips/Mips16FrameLowering.h

   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
+                                 DenseMap<int, int> &CSRSlots,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,

lib/Target/Mips/Mips16FrameLowering.cpp

 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MI,
                           const std::vector<CalleeSavedInfo> &CSI,
+                          DenseMap<int, int> &CSRSlots,
                           const TargetRegisterInfo *TRI) const {
   MachineFunction *MF = MBB.getParent();
   MachineBasicBlock *EntryBlock = MF->begin();

lib/Target/Mips/MipsSEFrameLowering.h

   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
+                                 DenseMap<int, int> &CSRSlots,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool hasReservedCallFrame(const MachineFunction &MF) const override;

lib/Target/Mips/MipsSEFrameLowering.cpp

 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MI,
                           const std::vector<CalleeSavedInfo> &CSI,
+                          DenseMap<int, int> &CSRSlots,
                           const TargetRegisterInfo *TRI) const {
   MachineFunction *MF = MBB.getParent();
   MachineBasicBlock *EntryBlock = MF->begin();

lib/Target/PowerPC/PPCFrameLowering.h

   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
+                                 DenseMap<int, int> &CSRSlots,
                                  const TargetRegisterInfo *TRI) const override;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,

lib/Target/PowerPC/PPCFrameLowering.cpp

 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator MI,
                                      const std::vector<CalleeSavedInfo> &CSI,
+                                     DenseMap<int, int> &CSRSlots,
                                      const TargetRegisterInfo *TRI) const {
 
   // Currently, this function only handles SVR4 32- and 64-bit ABIs.

lib/Target/SystemZ/SystemZFrameLowering.h

   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MBBI,
                                  const std::vector<CalleeSavedInfo> &CSI,
+                                 DenseMap<int, int> &CSRSlots,
                                  const TargetRegisterInfo *TRI) const override;
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MBBII,

lib/Target/SystemZ/SystemZFrameLowering.cpp

 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MBBI,
                           const std::vector<CalleeSavedInfo> &CSI,
+                          DenseMap<int, int> &CSRSlots,
                           const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;

lib/Target/X86/X86FrameLowering.h

   bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI,
                                  const std::vector<CalleeSavedInfo> &CSI,
+                                 DenseMap<int, int> &CSRSlots,
                                  const TargetRegisterInfo *TRI) const override;
 
   bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,

lib/Target/X86/X86FrameLowering.cpp

   // FIXME: This is dirty hack. The code itself is pretty mess right now.
   // It should be rewritten from scratch and generalized sometimes.
 
-  // Determine maximum offset (minimum due to stack growth).
-  int64_t MaxOffset = 0;
-  for (std::vector<CalleeSavedInfo>::const_iterator
-         I = CSI.begin(), E = CSI.end(); I != E; ++I)
-    MaxOffset = std::min(MaxOffset,
-                         MFI->getObjectOffset(I->getFrameIdx()));
-
-  // Calculate offsets.
-  int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
   for (std::vector<CalleeSavedInfo>::const_iterator
          I = CSI.begin(), E = CSI.end(); I != E; ++I) {
     int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
     unsigned Reg = I->getReg();
-    Offset = MaxOffset - Offset + saveAreaOffset;
 
     // Don't output a new machine move if we're re-saving the frame
     // pointer. This happens when the PrologEpilogInserter has inserted an extra

 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                              MachineBasicBlock::iterator MI,
                                         const std::vector<CalleeSavedInfo> &CSI,
+                                             DenseMap<int, int> &CSRSlots,
                                           const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return false;

   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
   const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
 
+  // Offset into the CSR area.
+  int CSRFrameOffset = 0;
+
   // Push GPRs. It increases frame size.
   unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
   for (unsigned i = CSI.size(); i != 0; --i) {

     CalleeFrameSize += SlotSize;
     BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
       .setMIFlag(MachineInstr::FrameSetup);
+    CSRFrameOffset -= SlotSize;
+    CSRSlots[CSI[i-1].getFrameIdx()] = CSRFrameOffset;
   }
 
   X86FI->setCalleeSavedFrameSize(CalleeFrameSize);

lib/Target/XCore/XCoreFrameLowering.h

     bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,
                                   const std::vector<CalleeSavedInfo> &CSI,
+                                  DenseMap<int, int> &CSRSlots,
                                   const TargetRegisterInfo *TRI) const override;
     bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator MI,

lib/Target/XCore/XCoreFrameLowering.cpp

 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MI,
                           const std::vector<CalleeSavedInfo> &CSI,
+                          DenseMap<int, int> &CSRSlots,
                           const TargetRegisterInfo *TRI) const {
   if (CSI.empty())
     return true;

test/CodeGen/X86/pr19905.ll

+; RUN: llc < %s -march=x86-64 -verify-machineinstrs | FileCheck %s
+
+declare void @llvm.eh.unwind.init()
+
+define coldcc void @calls_unwind_init() {
+; CHECK: pushq  %rbp
+; CHECK: .cfi_def_cfa_offset 16
+; CHECK: .cfi_offset %rbp, -16
+; CHECK: movq %rsp, %rbp
+; CHECK: .cfi_def_cfa_register %rbp
+; CHECK: pushq  %r15
+; CHECK: pushq  %r14
+; CHECK: pushq  %r13
+; CHECK: pushq  %r12
+; CHECK: pushq  %r11
+; CHECK: pushq  %r10
+; CHECK: pushq  %r9
+; CHECK: pushq  %r8
+; CHECK: pushq  %rdi
+; CHECK: pushq  %rsi
+; CHECK: pushq  %rdx
+; CHECK: pushq  %rcx
+; CHECK: pushq  %rbx
+; CHECK: subq $136, %rsp
+
+; These are supposed to be offsets from the CFA, which is the value of
+; stack pointer just before the call.  %rbx is the 14th register we
+; explicitly push, including %rbp, so this offset is -8 (for the
+; return address) + 14 * -8 = -120
+
+; CHECK: .cfi_offset %rbx, -120
+; CHECK: .cfi_offset %rcx, -112
+; CHECK: .cfi_offset %rdx, -104
+; CHECK: .cfi_offset %rsi, -96
+; CHECK: .cfi_offset %rdi, -88
+; CHECK: .cfi_offset %r8, -80
+; CHECK: .cfi_offset %r9, -72
+; CHECK: .cfi_offset %r10, -64
+; CHECK: .cfi_offset %r11, -56
+; CHECK: .cfi_offset %r12, -48
+; CHECK: .cfi_offset %r13, -40
+; CHECK: .cfi_offset %r14, -32
+; CHECK: .cfi_offset %r15, -24
+; CHECK: .cfi_offset %xmm0, -144
+; CHECK: .cfi_offset %xmm1, -160
+; CHECK: .cfi_offset %xmm2, -176
+; CHECK: .cfi_offset %xmm3, -192
+; CHECK: .cfi_offset %xmm4, -208
+; CHECK: .cfi_offset %xmm5, -224
+; CHECK: .cfi_offset %xmm6, -240
+; CHECK: .cfi_offset %xmm7, -256
+; CHECK: .cfi_offset %xmm8, -272
+; CHECK: .cfi_offset %xmm9, -288
+; CHECK: .cfi_offset %xmm10, -304
+; CHECK: .cfi_offset %xmm11, -320
+; CHECK: .cfi_offset %xmm12, -336
+; CHECK: .cfi_offset %xmm13, -352
+; CHECK: .cfi_offset %xmm14, -368
+; CHECK: .cfi_offset %xmm15, -384
+; CHECK: movaps %xmm15, -368(%rbp)      # 16-byte Spill
+; CHECK: movaps %xmm14, -352(%rbp)      # 16-byte Spill
+; CHECK: movaps %xmm13, -336(%rbp)      # 16-byte Spill
+; CHECK: movaps %xmm12, -320(%rbp)      # 16-byte Spill
+; CHECK: movaps %xmm11, -304(%rbp)      # 16-byte Spill
+; CHECK: movaps %xmm10, -288(%rbp)      # 16-byte Spill
+; CHECK: movaps %xmm9, -272(%rbp)       # 16-byte Spill
+; CHECK: movaps %xmm8, -256(%rbp)       # 16-byte Spill
+; CHECK: movaps %xmm7, -240(%rbp)       # 16-byte Spill
+; CHECK: movaps %xmm6, -224(%rbp)       # 16-byte Spill
+; CHECK: movaps %xmm5, -208(%rbp)       # 16-byte Spill
+; CHECK: movaps %xmm4, -192(%rbp)       # 16-byte Spill
+; CHECK: movaps %xmm3, -176(%rbp)       # 16-byte Spill
+; CHECK: movaps %xmm2, -160(%rbp)       # 16-byte Spill
+; CHECK: movaps %xmm1, -144(%rbp)       # 16-byte Spill
+; CHECK: movaps %xmm0, -128(%rbp)       # 16-byte Spill
+
+  call void @llvm.eh.unwind.init()
+  ret void
+}