[SystemZ] set 'guessInstructionProperties = 0' and add flags as needed.

[jonpa]

Summary

After setting 'guessInstructionProperties = 0', mayLoad, mayStore and hasSideEffects have been set to 0 per default in InstSystemZ.

Then those flags have been set on individual instructions so that there is no diff on the tablegen output compared to trunk.

I suspect that null_fag may have set this flag earlier in places where we could now remove it.

Not sure why, but SRAK seems to have the SideEffects flag...

hasSideEffects = 0 could also be removed in a few places.

[uweigand]

Thanks for looking at and reviewing those flags!

It's a good first step to ensure that flags remain identical to what they currently are. However, this seems to have exposed a couple of bugs in the current flags. Let's see what the best way to get to a correct solution is, without introducing too many intermediate changes ... I'm now wondering whether we should first fix wrong flags and then switch to guessInstructionProperties = 0 or the other way around.

First of all, I'm not sure it makes much sense to introduce "generic" settings of hasSideEffects in instruction format patterns. You've added them to all SideEffect* patterns -- however, while all those instructions have "side effects" in the sense that they not only operate on their operands, the many (most?) cases those side effect are simply memory accesses (loads or stores), which should already be handled via mayLoad / mayStore. Those should *not* also have hasSideEffects set; that flag is only needed if there are any *other* "unmodeled" side effects. I think I added the correct mayLoad/mayStore/hasSideEffects setting to all (I hope!) SideEffect* pattersn, but I didn't realize I had to actively reset hasSideEffects to zero. So I guess it is OK to add the flag to the SideEffect* patterns for now to ensure we get NFC, but then later on remove them all again, since they're actually incorrect. (Possibly doing another review of all users first.)

A similar issue are the "generic" vector instructions (i.e. the *Generic patterns). Those are all inline-assembler-only patterns, and therefore have no DAG pattern (which I guess is why they were classified as hasSideEffects by the default logic). You seem to have added the flag to some but not all *Generic patterns, but for those patterns where you haven't added it you instead added it to the instructions that use it ... Similar to above, I think it is OK to add the flag for now, but then you should just add it to *all* Generic patterns, to avoid unnecessary changes to the vector instruction patterns.

Yet again similar are the *K patterns. There the hasSideEffects flags is pretty much always wrong, it's just added incorrectly because the patterns use null_frag. Again, I'm fine with temporarily adding and later removing it. However, the duplication of the BinaryRSAndK pattern seems weird. Is this because some users of BinaryRSAndK manually set hasSideEffects = 0? This was probably already an attempt to work around. They should just *all* use that ...

The final major issue seem to be the HFP (hex floating-point) and DFP (decimal floating-point) settings. I guess they all have hasSideEffects because they are never used for code generation and therefore all use null_frag. Now I thought that floating-point operations usually have side effects anyway since they may trap. But that doesn't seem to be even modeled for the normal (binary) floating-point instructions, where it would be most important since those are actually used for codegen ... Not sure if this hides a bug somewhere. On the other hand, other platforms don't appear to set this for FP instructions either, so I guess we should leave it for now. But then we should probably treat HFP and DFP the same.

I've gone through the changes in detail. Note that my comments really refer to the state we should have in the end, i.e. in most cases *different* from the current setting. Given that we'd have to introduce many changes to those files just to revert them again, maybe in would be better to do the changes in a single step after all ...

lib/Target/SystemZ/SystemZInstrDFP.td

20 ↗

(On Diff #124194)

Given the discussion above, the comment should probably be different.

lib/Target/SystemZ/SystemZInstrFP.td

139

This shouldn't have hasSideEffects = 1, but rather mayLoad = 1. This would fix a current bug.

Note that the whole block of load instructions really should have mayLoad = 1.

160

Again, probably best if the whole block is marked mayStore = 1.

182

These aren't really different from other FP instructions, so if the rest don't have hasSideEffects = 1, this shouldn't either ... The same comment actually applies to the rest of these changes throughout this file.

529–532

These are actually wrong: EFPC and SFPC do not touch memory at all, while STFPC is only a store and LFPC is only a load. I think this is wrongly inferred because the definition of the int_s390_efpc / int_s390_sfpc intrinsics in include/llvm/IR/IntrinsicsSystemZ.td is wrong: they should be marked as IntrNoMem. (This specific problem can just be fixed before, I think.)

lib/Target/SystemZ/SystemZInstrFormats.td

4509

This is certainly also wrong, those compares have no special side effects ...

lib/Target/SystemZ/SystemZInstrInfo.td

14–16

Since those are fully no-op on SystemZ, they have no side effects.

39

I believe as long as branches are correctly marked as isBranch, they don't need to *also* carry a hasSideEffects flag.

201

But traps certainly should, so this one is fine.

375

This is a no-op and has no side effects.

376

This has no side effects.

411

Probably best to mark the whole block as mayLoad = 1.

455

Same here, mark the whole block as mayStore = 1.

515

This doesn't have side effects, just a mayStore ...

528

These should actually match the mayLoad / mayStore settings of the underlying instructions.

583

Doesn't actually have any side effects.

684

Doesn't have side effects.

696

Likewise.

733

Should just be mayStore.

743

Should be mayLoad / mayStore as appropriate, has no other side effects.

847

Should just be mayLoad.

906

No side effects with any of the adds. The to-memory variants should be mayLoad and mayStore.

1029

No side effects.

1033

Neither here. Why are SLFI and SLGFI different in the first place, that's weird ...

1249

No side effects on any of the multiplies ...

1327

As discussed above, none of the shifts or rotates has side effects.

1401

No side effects.

1453

Likewise.

1529

Just mayLoad

1543

This is actually fine, I guess.

1569

Should just have mayLoad/mayStore, like the others. Maybe for the whole block?

1702

Hmm. Not sure if atomics should have the SideEffect marker ... but either all of them or none.

1750

Just mayLoad is enough.

1816

mayLoad should be enough for these. (They may trap, but so can any load ...)

1828

Just mayLoad or mayStore

1863

Just mayLoad

1875

No particular side effects for the access register routines (except mayLoad / mayStore as appropriate)

1905

As above, no side effects for branches.

1939

This really should only be a mayStore. Maybe another bug in the intrinsics definition.

1947–1949

A TABORT is probably best genuinely marked as hasSideEffects = 1. It shouldn't be mayLoad or mayStore.

1953

Should be store only.

1979

No side effects.

2025

This is OK.

lib/Target/SystemZ/SystemZInstrSystem.td

63–66

This as well.

186

Not really. None of the remaining changes in this file look good.

lib/Target/SystemZ/SystemZInstrVector.td

19

Nothing in this file really should have hasSideEffects = 1.

214

No, this should just be mayStore. Another intrinsics issue?

245

Likewise.

[jonpa]

Still NFC.

Patch updated to minimize changes in SystemZInstrVector.td, by moving the flag settings to the *Generic classes instead.

[jonpa]

Patch updated per review, with functional changes.

Three SystemZ tests have been updated, where two of them now have an extra COPY (instructions may now be more freely rescheduled). Hopefully, this should go away with other ongoing patches. One SystemZ test is crashing (asm-18.ll), see llvm-dev for explanation of the TwoAddress problem.

Hopefully, it should be possible to observe the changes by diffing to the previous diff, which was NFC.

lib/Target/SystemZ/SystemZInstrDFP.td

20 ↗

(On Diff #124194)

I removed the hasSideEffects flag in both DFP/HFP to be consistent , and instead made a TODO comment about perhaps adding this flag to all relevant FP instructions.

lib/Target/SystemZ/SystemZInstrFP.td

529–532

Not sure exactly how to do this - there is only one intrinsic (for read/set), but two instructions, where only one of them loads/stores.

It does not compile if just setting mayLoad=0, mayStore=0 on the non-mem instructions.

Would it work to add duplicate intrinsics for this in InstrinsicsSystemZ.td, like

 def int_s390_sfpc : GCCBuiltin<"__builtin_s390_sfpc">,
                      Intrinsic<[], [llvm_i32_ty], [IntrNoMem]>;

 def int_s390_sfpc_mem : GCCBuiltin<"__builtin_s390_sfpc">,
                          Intrinsic<[], [llvm_i32_ty], []>;
...

Or is this so rare that it could be ignored and left alone?

lib/Target/SystemZ/SystemZInstrInfo.td

14–16

Tried to remove, but did not work due to the callseq_... nodes in the pattern.

1033

yes... I don't know really

1702

Since we are unsure, I put all inside a new block with this flag set, and added a TODO comment regarding this. This is now *all* instructions in the atomic section, not just the ATOMIC instructions. Is that what you meant?

1905

OK - I am assuming this should also work the same for isCall / isReturn

1939

Yes. I tried to experiment with the intrinsics declarations like adding WriteOnly<0> and so on, but to no other effect than very long rebuild times...

I am leaving these flags as they are now as they are forced by the intrinsics definitions...

lib/Target/SystemZ/SystemZInstrVector.td

19

I suppose the vector FP instructions still follow the same discussion as for the FP files?

214

most likely -- leaving as for the others above.

[jonpa]

flagsdiff_master.diff167 KBDownload

This file is the output of a simple script I made, to perhaps get a better overview of the functional changes for the instructions.

[uweigand]

Thanks for providing the diff. I noticed two problems, also annotated in the detailed comment:

• You added mayLoad to a number of load-conditional instructions that actually don't access memory (reg-reg or reg-immed instructions)
• The guarded-storage instructions should really have the side effects flag (I overlooked this in my previous review).

The rest of the changes looks OK to me.

As to your question:

I suppose the vector FP instructions still follow the same discussion as for the FP files?

Yes, this is true.

lib/Target/SystemZ/SystemZInstrInfo.td

92

This should better be in the FixedCondBranchRXY pattern -- this already hard-codes the "load" DAG node, so it can also hard-code mayLoad. B.t.w. the other CondBranchRXY pattern variants really also should have the mayLoad flag ...

528

Most of these are load immediate or load register instructions, they do not access memory.

536

Only this one should have mayLoad.

556

Again, the first two are load register instructions, only the second two should have mayLoad.

927

Do we need this? Should be correctly autodetected from the DAG patterns. The same applied to various patterns below.

931

This is already in BinarySIY. Same applies to other BinarySIY patterns.

1810–1815

Thinking about this, the whole set of FeatureGuardedStorage instructions should have the HasSideEffects flags after all, since they use and/or modify the guarded storage control registers, which we do not otherwise model, so the must not be reordered with respect to each other.

[jonpa]

Updated per review.

The bugfix in TwoAddress is under review separately. Only the test case here will be committed by this patch, as it exposes the bug.

With the bugfix I could build benchmarks and I saw just some minor differences in instruction counts:

tmll           :                15798                15987     +189
lr             :                25915                25769     -146
wfsdb          :                 6655                 6795     +140
sdbr           :                 3134                 2994     -140
j              :                98539                98678     +139
nr             :                 2845                 2709     -136
n              :                 8918                 9052     +134
tmhl           :                  933                  799     -134
risbhg         :                 1996                 1880     -116
ldr            :                22280                22172     -108
stg            :               124184               124093      -91
lg             :               317058               316968      -90
lt             :                 7152                 7072      -80
cgrjlh         :                11594                11673      +79
risblg         :                 8448                 8527      +79
l              :                65752                65830      +78
st             :                51556                51628      +72
mdbr           :                 6686                 6615      -71
risbgn         :                34903                34837      -66

                 spec-llvm_A_clang-master/            spec-llvm
Spill|Reload   :               164860               164772      -88

Reduced spilling should be a good indicator.

lib/Target/SystemZ/SystemZInstrInfo.td

92

I added 'mayLoad = 1' to the three *CondBranchRXY patterns. This added the mayLoad flag on BIAsm* and BIC[Asm] instructions.

536

removed the mayLoad setting - FixedCondUnaryRSY already hard codes it.

556

Oops. Again removed the mayLoad = 1 flag, as it is already hard coded. I assume this to be the policy, so I also removed mayStore from STOC* instructions.

931

OK - I am guessing then that if the instruction class sets the mayLoad / mayStore flag, it should preferrably not also be set on the instruction. I tried to clean away the cases I could find in this file. I suppose the other files could also be cleaned up?

[uweigand]

These changes (at the code level) look reasonable to me now. (There is one mayStore on a STOC instruction that is probably still superfluous now.)

I've looked again at the atomic instructions, and I now think they should not have the "unmodelled side effects" flags: they do have side effects, but those are modeled (e.g. via the ordering flags). Common code should (and as far as I can tell, does) look at those properties to decide whether and how an atomic instruction may be scheduled. This also matches the fact that most of the atomics didn't have hasSideEffects before your patch, and they don't on other platforms either. So I think they should simply not have the flag.

Otherwise, there's still two things that should be fixed before this can go in: the TwoAddress fix, and the intrinsics flags.

Once this is all ready, could you please re-create another diff for the attribute settings, just so we can verify that nothing surprising has crept in? Thanks!

lib/Target/SystemZ/SystemZInstrInfo.td

528

Shouldn't this be unnecessary as well?

[jonpa]

Path updated.

Functional change:

UnmodeledSideEffects REMOVED: ATOMIC_CMP_SWAPW, ATOMIC_LOADW_AFI, ATOMIC_LOADW_AR, ATOMIC_LOADW_MAX, ATOMIC_LOADW_MIN, ATOMIC_LOADW_NILH, ATOMIC_LOADW_NILHi, ATOMIC_LOADW_NR, ATOMIC_LOADW_NRi, ATOMIC_LOADW_OILH, ATOMIC_LOADW_OR, ATOMIC_LOADW_SR, ATOMIC_LOADW_UMAX, ATOMIC_LOADW_UMIN, ATOMIC_LOADW_XILF, ATOMIC_LOADW_XR, ATOMIC_LOAD_AFI, ATOMIC_LOAD_AGFI, ATOMIC_LOAD_AGHI, ATOMIC_LOAD_AGR, ATOMIC_LOAD_AHI, ATOMIC_LOAD_AR, ATOMIC_LOAD_MAX_32, ATOMIC_LOAD_MAX_64, ATOMIC_LOAD_MIN_32, ATOMIC_LOAD_MIN_64, ATOMIC_LOAD_NGR, ATOMIC_LOAD_NGRi, ATOMIC_LOAD_NIHF64, ATOMIC_LOAD_NIHF64i, ATOMIC_LOAD_NIHH64, ATOMIC_LOAD_NIHH64i, ATOMIC_LOAD_NIHL64, ATOMIC_LOAD_NIHL64i, ATOMIC_LOAD_NILF, ATOMIC_LOAD_NILF64, ATOMIC_LOAD_NILF64i, ATOMIC_LOAD_NILFi, ATOMIC_LOAD_NILH, ATOMIC_LOAD_NILH64, ATOMIC_LOAD_NILH64i, ATOMIC_LOAD_NILHi, ATOMIC_LOAD_NILL, ATOMIC_LOAD_NILL64, ATOMIC_LOAD_NILL64i, ATOMIC_LOAD_NILLi, ATOMIC_LOAD_NR, ATOMIC_LOAD_NRi, ATOMIC_LOAD_OGR, ATOMIC_LOAD_OIHF64, ATOMIC_LOAD_OIHH64, ATOMIC_LOAD_OIHL64, ATOMIC_LOAD_OILF, ATOMIC_LOAD_OILF64, ATOMIC_LOAD_OILH, ATOMIC_LOAD_OILH64, ATOMIC_LOAD_OILL, ATOMIC_LOAD_OILL64, ATOMIC_LOAD_OR, ATOMIC_LOAD_SGR, ATOMIC_LOAD_SR, ATOMIC_LOAD_UMAX_32, ATOMIC_LOAD_UMAX_64, ATOMIC_LOAD_UMIN_32, ATOMIC_LOAD_UMIN_64, ATOMIC_LOAD_XGR, ATOMIC_LOAD_XIHF64, ATOMIC_LOAD_XILF, ATOMIC_LOAD_XILF64, ATOMIC_LOAD_XR, ATOMIC_SWAPW, ATOMIC_SWAP_32, ATOMIC_SWAP_64, CDS, CDSG, CDSY, CS, CSG, CSST, CSY, LAA, LAAG, LAAL, LAALG, LAN, LANG, LAO, LAOG, LAX, LAXG, LPD, LPDG, LPQ, PLO, STPQ, TS.

Otherwise, there's still two things that should be fixed before this can go in: the TwoAddress fix, and the intrinsics flags.

The TwoAddress fix has been committed, but the intrinsics flags fixing seem to require some work so I am not sure if we really want to wait with these changes until that is done?

Once this is all ready, could you please re-create another diff for the attribute settings, just so we can verify that nothing surprising has crept in?

Sure, this should be an updated diff of the patch effects:

flagsdiff_master_dec4156 KBDownload

[jonpa]

lib/Target/SystemZ/SystemZInstrInfo.td

528

Yes - removed this one and a few more in SystemZInstrSystem.td with NFC.

[uweigand]

The TwoAddress fix has been committed, but the intrinsics flags fixing seem to require some work so I am not sure if we really want to wait with these changes until that is done?

The problems with the intrinsics flags were related to IntrNoMem, right? This only happens for a few of the changes, the majority were about IntrWriteMem IIRC. It should be possible to add at least those changes right away without problem. And that would already remove the need for many of the wrongly-added mayLoad = 1 settings in this patch ...

Otherwise, this all looks good to me now.

[jonpa]

The TwoAddress fix has been committed, but the intrinsics flags fixing seem to require some work so I am not sure if we really want to wait with these changes until that is done?

The problems with the intrinsics flags were related to IntrNoMem, right? This only happens for a few of the changes, the majority were about IntrWriteMem IIRC. It should be possible to add at least those changes right away without problem. And that would already remove the need for many of the wrongly-added mayLoad = 1 settings in this patch ...

Yes, the IntrHasSideEffects would be needed for IntrNoMem (tabort, sfpc, efpc).

Patch updated for the other cases by adding IntrWriteMem and removing mayLoad flags, with functional change:

MayLoad REMOVED: NTSTG, TBEGINC, VSTL, VSTRL, VSTRLR

[uweigand]

For consistency, the other variants of the tbegin intrinsic (int_s390_tbegin and int_s390_tbegin_nofloat) should likewise get the IntrWriteMem flag.

Otherwise, this LGTM now. Thanks!

[jonpa]

r319756

include/llvm/IR/IntrinsicsSystemZ.td

let TargetPrefix = "s390" in {
   def int_s390_tbegin : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
                                   [IntrNoDuplicate]>;
 
   def int_s390_tbegin_nofloat : Intrinsic<[llvm_i32_ty],
                                           [llvm_ptr_ty, llvm_i32_ty],
                                           [IntrNoDuplicate]>;
 
   def int_s390_tbeginc : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
-                                   [IntrNoDuplicate]>;
+                                   [IntrNoDuplicate, IntrWriteMem]>;
 
   def int_s390_tabort : Intrinsic<[], [llvm_i64_ty],
                                   [IntrNoReturn, Throws]>;
 
   def int_s390_tend : GCCBuiltin<"__builtin_tend">,
                       Intrinsic<[llvm_i32_ty], []>;
 
   def int_s390_etnd : GCCBuiltin<"__builtin_tx_nesting_depth">,
                       Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
 
   def int_s390_ntstg : Intrinsic<[], [llvm_i64_ty, llvm_ptr64_ty],
-                                 [IntrArgMemOnly]>;
+                                 [IntrArgMemOnly, IntrWriteMem]>;
 
   def int_s390_ppa_txassist : GCCBuiltin<"__builtin_tx_assist">,
                               Intrinsic<[], [llvm_i32_ty]>;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // Vector intrinsics
let TargetPrefix = "s390" in {
   defm int_s390_vpks : SystemZBinaryTruncHFG<"vpks">;
   defm int_s390_vpks : SystemZBinaryTruncCCHFG;
 
   defm int_s390_vpkls : SystemZBinaryTruncHFG<"vpkls">;
   defm int_s390_vpkls : SystemZBinaryTruncCCHFG;
 
   def int_s390_vstl : GCCBuiltin<"__builtin_s390_vstl">,
                       Intrinsic<[], [llvm_v16i8_ty, llvm_i32_ty, llvm_ptr_ty],
-                                // In fact write-only but there's no property
-                                // for that.
-                                [IntrArgMemOnly]>;
+                                [IntrArgMemOnly, IntrWriteMem]>;
 
   defm int_s390_vupl  : SystemZUnaryExtBHWF<"vupl">;
   defm int_s390_vupll : SystemZUnaryExtBHF<"vupll">;
 
   defm int_s390_vuph  : SystemZUnaryExtBHF<"vuph">;
   defm int_s390_vuplh : SystemZUnaryExtBHF<"vuplh">;
 
   defm int_s390_vacc : SystemZBinaryBHFG<"vacc">;
let TargetPrefix = "s390" in {
 
   // Instructions from the Vector Packed Decimal Facility
   def int_s390_vlrl : GCCBuiltin<"__builtin_s390_vlrl">,
                       Intrinsic<[llvm_v16i8_ty], [llvm_i32_ty, llvm_ptr_ty],
                                 [IntrReadMem, IntrArgMemOnly]>;
 
   def int_s390_vstrl : GCCBuiltin<"__builtin_s390_vstrl">,
                        Intrinsic<[], [llvm_v16i8_ty, llvm_i32_ty, llvm_ptr_ty],
-                                 // In fact write-only but there's no property
-                                 // for that.
-                                 [IntrArgMemOnly]>;
+                                 [IntrArgMemOnly, IntrWriteMem]>;
 }
 
 //===----------------------------------------------------------------------===//
 //
 // Misc intrinsics
 //
 //===----------------------------------------------------------------------===//
 

lib/Target/SystemZ/SystemZ.td

 include "SystemZInstrFormats.td"
 include "SystemZInstrInfo.td"
 include "SystemZInstrVector.td"
 include "SystemZInstrFP.td"
 include "SystemZInstrHFP.td"
 include "SystemZInstrDFP.td"
 include "SystemZInstrSystem.td"
 
-def SystemZInstrInfo : InstrInfo {}
+def SystemZInstrInfo : InstrInfo { let guessInstructionProperties = 0; }
 
 //===----------------------------------------------------------------------===//
 // Assembly parser
 //===----------------------------------------------------------------------===//
 
 def SystemZAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;
 }

lib/Target/SystemZ/SystemZInstrFP.td

 //==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
+// TODO: Most floating-point instructions (except for simple moves and the
+// like) can raise exceptions -- should they have hasSideEffects=1 ?
+
 //===----------------------------------------------------------------------===//
 // Select instructions
 //===----------------------------------------------------------------------===//
 
 // C's ?: operator for floating-point operands.
 def SelectF32  : SelectWrapper<f32, FP32>;
 def SelectF64  : SelectWrapper<f64, FP64>;
 let Predicates = [FeatureNoVectorEnhancements1] in
   def SelectF128 : SelectWrapper<f128, FP128>;
 let Predicates = [FeatureVectorEnhancements1] in
   def SelectVR128 : SelectWrapper<f128, VR128>;
 
 defm CondStoreF32 : CondStores<FP32, nonvolatile_store,
                                nonvolatile_load, bdxaddr20only>;
 defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
                                nonvolatile_load, bdxaddr20only>;
 
 //===----------------------------------------------------------------------===//
 // Move instructions
 //===----------------------------------------------------------------------===//
 
 // Load zero.
-let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1 in {
+let isAsCheapAsAMove = 1, isMoveImm = 1 in {
   def LZER : InherentRRE<"lzer", 0xB374, FP32,  fpimm0>;
   def LZDR : InherentRRE<"lzdr", 0xB375, FP64,  fpimm0>;
   def LZXR : InherentRRE<"lzxr", 0xB376, FP128, fpimm0>;
 }
 
 // Moves between two floating-point registers.
-let hasSideEffects = 0 in {
-  def LER : UnaryRR <"ler", 0x38,   null_frag, FP32,  FP32>;
-  def LDR : UnaryRR <"ldr", 0x28,   null_frag, FP64,  FP64>;
-  def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;
 
-  // For z13 we prefer LDR over LER to avoid partial register dependencies.
-  let isCodeGenOnly = 1 in
-    def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
-}
 
 // Moves between two floating-point registers that also set the condition
 // codes.
 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
   defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>;
   defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>;
   defm LTXBR : LoadAndTestRRE<"ltxbr", 0xB342, FP128>;
 }

 defm LoadStoreF32  : MVCLoadStore<load, f32,  MVCSequence, 4>;
 defm LoadStoreF64  : MVCLoadStore<load, f64,  MVCSequence, 8>;
 defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
 
 //===----------------------------------------------------------------------===//
 // Load instructions
 //===----------------------------------------------------------------------===//
 
-let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
+let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
   defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
   defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;
 
   // For z13 we prefer LDE over LE to avoid partial register dependencies.
   let isCodeGenOnly = 1 in
     def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>;
 
   // These instructions are split after register allocation, so we don't
   // want a custom inserter.
   let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
     def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
                      [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
   }
 }
 
 //===----------------------------------------------------------------------===//
 // Store instructions
 //===----------------------------------------------------------------------===//
 
-let SimpleBDXStore = 1 in {
+let SimpleBDXStore = 1, mayStore = 1 in {
   defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
   defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;
 
   // These instructions are split after register allocation, so we don't
   // want a custom inserter.
   let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
     def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
                      [(store FP128:$src, bdxaddr20only128:$dst)]>;
   }
 }
 
 //===----------------------------------------------------------------------===//
 // Conversion instructions
 //===----------------------------------------------------------------------===//
 
 // Convert floating-point values to narrower representations, rounding
 // according to the current mode.  The destination of LEXBR and LDXBR
 // is a 128-bit value, but only the first register of the pair is used.
 def LEDBR : UnaryRRE<"ledbr", 0xB344, fpround,    FP32,  FP64>;
 def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>;
 def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>;
 
 def LEDBRA : TernaryRRFe<"ledbra", 0xB344, FP32,  FP64>,
              Requires<[FeatureFPExtension]>;
 def LEXBRA : TernaryRRFe<"lexbra", 0xB346, FP128, FP128>,
              Requires<[FeatureFPExtension]>;
 def LDXBRA : TernaryRRFe<"ldxbra", 0xB345, FP128, FP128>,
              Requires<[FeatureFPExtension]>;
 
 let Predicates = [FeatureNoVectorEnhancements1] in {
   def : Pat<(f32 (fpround FP128:$src)),
             (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>;
   def : Pat<(f64 (fpround FP128:$src)),
             (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;
 }
 
let Defs = [CC], CCValues = 0xC in {
   def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>;
 }
 
 //===----------------------------------------------------------------------===//
 // Floating-point control register instructions
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 1 in {
+  let mayLoad = 1, mayStore = 1 in {
+    // TODO: EFPC and SFPC do not touch memory at all
     def EFPC  : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>;
     def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>;
 
     def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>;
     def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>;
+  }
 
   def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>;
   def LFAS  : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>;
 
   def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>,
               Requires<[FeatureFPExtension]>;
   def SRNM  : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>;
   def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>;

lib/Target/SystemZ/SystemZInstrFormats.td

class InstSystemZ<int size, dag outs, dag ins, string asmstr,
   let Namespace = "SystemZ";
 
   dag OutOperandList = outs;
   dag InOperandList = ins;
   let Size = size;
   let Pattern = pattern;
   let AsmString = asmstr;
 
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 0;
+
   // Some instructions come in pairs, one having a 12-bit displacement
   // and the other having a 20-bit displacement.  Both instructions in
   // the pair have the same DispKey and their DispSizes are "12" and "20"
   // respectively.
   string DispKey = "";
   string DispSize = "none";
 
   // Many register-based <INSN>R instructions have a memory-based <INSN>
class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
   let isAsmParserOnly = V.alternate;
   let M1 = V.ccmask;
 }
 
 class CondBranchRXY<string mnemonic, bits<16> opcode>
   : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
              !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
   let CCMaskFirst = 1;
+  let mayLoad = 1;
 }
 
 class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
   : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
-             mnemonic#"\t$M1, $XBD2", []>;
+             mnemonic#"\t$M1, $XBD2", []> {
+  let mayLoad = 1;
+}
 
 class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
                          SDPatternOperator operator = null_frag>
   : InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2),
              !subst("#", V.suffix, mnemonic)#"\t$XBD2",
              [(operator (load bdxaddr20only:$XBD2))]> {
   let isAsmParserOnly = V.alternate;
   let M1 = V.ccmask;
+  let mayLoad = 1;
 }
 
 class CmpBranchRIEa<string mnemonic, bits<16> opcode,
                     RegisterOperand cls, Immediate imm>
   : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
              mnemonic#"$M3\t$R1, $I2", []>;
 
 class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
                             SDPatternOperator operator,
                             RegisterOperand cls, bits<5> bytes,
                             AddressingMode mode = bdaddr20only> {
   let isCodeGenOnly = 1 in
     def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
   def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
 }
 
-
 class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
               RegisterOperand cls, bits<5> bytes,
               AddressingMode mode = bdxaddr12only>
   : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
             mnemonic#"\t$R1, $XBD2",
             [(set cls:$R1, (operator mode:$XBD2))]> {
   let OpKey = mnemonic#"r"#cls;
   let OpType = "mem";

 
 // A floating-point load-and test operation.  Create both a normal unary
 // operation and one that acts as a comparison against zero.
 // Note that the comparison against zero operation is not available if we
 // have vector support, since load-and-test instructions will partially
 // clobber the target (vector) register.
 multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
                           RegisterOperand cls> {
   def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
   let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
     def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
 }
 
 //===----------------------------------------------------------------------===//
 // Pseudo instructions
 //===----------------------------------------------------------------------===//
 //
class SelectWrapper<ValueType vt, RegisterOperand cls>
   // across them.
   let Defs = [CC];
   let Uses = [CC];
 }
 
 // Stores $new to $addr if $cc is true ("" case) or false (Inv case).
 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
                       SDPatternOperator load, AddressingMode mode> {
-  let Defs = [CC], Uses = [CC], usesCustomInserter = 1 in {
+  let Defs = [CC], Uses = [CC], usesCustomInserter = 1,
+      mayLoad = 1, mayStore = 1 in {
     def "" : Pseudo<(outs),
                     (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
                     [(store (z_select_ccmask cls:$new, (load mode:$addr),
                                              imm32zx4:$valid, imm32zx4:$cc),
                             mode:$addr)]>;
     def Inv : Pseudo<(outs),
                      (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
                      [(store (z_select_ccmask (load mode:$addr), cls:$new,

lib/Target/SystemZ/SystemZInstrInfo.td

 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Stack allocation
 //===----------------------------------------------------------------------===//
 
-let hasNoSchedulingInfo = 1 in {
+// The callseq_start node requires the hasSideEffects flag, even though these
+// instructions are noops on SystemZ.
+let hasNoSchedulingInfo = 1, hasSideEffects = 1 in {
   def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
                                 [(callseq_start timm:$amt1, timm:$amt2)]>;
   def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
                                 [(callseq_end timm:$amt1, timm:$amt2)]>;
 }
 
-let hasSideEffects = 0 in {
-  // Takes as input the value of the stack pointer after a dynamic allocation
-  // has been made.  Sets the output to the address of the dynamically-
-  // allocated area itself, skipping the outgoing arguments.
-  //
-  // This expands to an LA or LAY instruction.  We restrict the offset
-  // to the range of LA and keep the LAY range in reserve for when
-  // the size of the outgoing arguments is added.
-  def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
-                           [(set GR64:$dst, dynalloc12only:$src)]>;
-}
+
 
 //===----------------------------------------------------------------------===//
 // Branch instructions
 //===----------------------------------------------------------------------===//
 
 // Conditional branches.
 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
   // It's easier for LLVM to handle these branches in their raw BRC/BRCL form
   // with the condition-code mask being the first operand.  It seems friendlier
   // to use mnemonic forms like JE and JLH when writing out the assembly though.
   let isCodeGenOnly = 1 in {
     // An assembler extended mnemonic for BRC.
     def BRC  : CondBranchRI <"j#",  0xA74, z_br_ccmask>;
     // An assembler extended mnemonic for BRCL.  (The extension is "G"
     // rather than "L" because "JL" is "Jump if Less".)

 // conditional branches with the condition mask set to "always".
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
   def J  : FixedCondBranchRI <CondAlways, "j",  0xA74, br>;
   def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>;
   let isIndirectBranch = 1 in {
     def B  : FixedCondBranchRX<CondAlways, "b",  0x47>;
     def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>;
     def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>,
              Requires<[FeatureMiscellaneousExtensions2]>;
   }
 }
 
 // NOPs.  These are again variants of the conditional branches,
 // with the condition mask set to "never".
 def NOP  : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
 def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
 
let isBranch = 1, isTerminator = 1 in {
   def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>;
 }
 
 //===----------------------------------------------------------------------===//
 // Trap instructions
 //===----------------------------------------------------------------------===//
 
 // Unconditional trap.
-let hasCtrlDep = 1 in
+let hasCtrlDep = 1, hasSideEffects = 1 in
   def Trap : Alias<4, (outs), (ins), [(trap)]>;
 
 // Conditional trap.
-let hasCtrlDep = 1, Uses = [CC] in
+let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in
   def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>;
 
 // Fused compare-and-trap instructions.
-let hasCtrlDep = 1 in {
+let hasCtrlDep = 1, hasSideEffects = 1 in {
   // These patterns work the same way as for compare-and-branch.
   defm CRT   : CmpBranchRRFcPair<"crt",   0xB972, GR32>;
   defm CGRT  : CmpBranchRRFcPair<"cgrt",  0xB960, GR64>;
   defm CLRT  : CmpBranchRRFcPair<"clrt",  0xB973, GR32>;
   defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>;
   defm CIT   : CmpBranchRIEaPair<"cit",   0xEC72, GR32, imm32sx16>;
   defm CGIT  : CmpBranchRIEaPair<"cgit",  0xEC70, GR64, imm64sx16>;
   defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>;

 defm CondStore64 : CondStores<GR64, nonvolatile_store,
                               nonvolatile_load, bdxaddr20only>;
 
 //===----------------------------------------------------------------------===//
 // Move instructions
 //===----------------------------------------------------------------------===//
 
 // Register moves.
-let hasSideEffects = 0 in {
-  // Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
-  def LRMux : UnaryRRPseudo<"lr", null_frag, GRX32, GRX32>,
-              Requires<[FeatureHighWord]>;
-  def LR  : UnaryRR <"lr",  0x18,   null_frag, GR32, GR32>;
-  def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
-}
+
 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
   def LTR  : UnaryRR <"ltr",  0x12,   null_frag, GR32, GR32>;
   def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>;
 }
 
 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
   def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>;
 
 // Immediate moves.
-let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
-    isReMaterializable = 1 in {
+let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
   // 16-bit sign-extended immediates.  LHIMux expands to LHI or IIHF,
   // deopending on the choice of register.
   def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
                Requires<[FeatureHighWord]>;
   def LHI  : UnaryRI<"lhi",  0xA78, bitconvert, GR32, imm32sx16>;
   def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
 
   // Other 16-bit immediates.
   def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
   def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
   def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
   def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
 
   // 32-bit immediates.
   def LGFI  : UnaryRIL<"lgfi",  0xC01, bitconvert, GR64, imm64sx32>;
   def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
   def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
 }
 
 // Register loads.
-let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
+let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
   // Expands to L, LY or LFH, depending on the choice of register.
   def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
              Requires<[FeatureHighWord]>;
   defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
   def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
             Requires<[FeatureHighWord]>;
   def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
 
   // These instructions are split after register allocation, so we don't
   // want a custom inserter.
   let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
     def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
                       [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
   }
 }
 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
   def LT  : UnaryRXY<"lt",  0xE312, load, GR32, 4>;
   def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
 }
let Predicates = [FeatureLoadAndZeroRightmostByte] in {
   def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>;
   def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00),
             (LZRF bdxaddr20only:$src)>;
   def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00),
             (LZRG bdxaddr20only:$src)>;
 }
 
 // Load and trap.
-let Predicates = [FeatureLoadAndTrap] in {
+let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {
   def LAT   : UnaryRXY<"lat",   0xE39F, null_frag, GR32, 4>;
   def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>;
   def LGAT  : UnaryRXY<"lgat",  0xE385, null_frag, GR64, 8>;
 }
 
 // Register stores.
-let SimpleBDXStore = 1 in {
+let SimpleBDXStore = 1, mayStore = 1 in {
   // Expands to ST, STY or STFH, depending on the choice of register.
   def STMux : StoreRXYPseudo<store, GRX32, 4>,
               Requires<[FeatureHighWord]>;
   defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
   def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
              Requires<[FeatureHighWord]>;
   def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
 
   // These instructions are split after register allocation, so we don't
   // want a custom inserter.
   let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
     def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
                        [(store GR128:$src, bdxaddr20only128:$dst)]>;
   }
 }
 def STRL  : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
 
 // 8-bit immediate stores to 8-bit fields.

 
 //===----------------------------------------------------------------------===//
 // Conditional move instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in {
   // Load immediate on condition.  Matched via DAG pattern and created
   // by the PeepholeOptimizer via FoldImmediate.
-  let hasSideEffects = 0 in {
-    // Expands to LOCHI or LOCHHI, depending on the choice of register.
-    def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>;
-    defm LOCHHI  : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>;
-    defm LOCHI   : CondBinaryRIEPair<"lochi",  0xEC42, GR32, imm32sx16>;
-    defm LOCGHI  : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>;
-  }
+
 
   // Move register on condition.  Expanded from Select* pseudos and
   // created by early if-conversion.
-  let hasSideEffects = 0, isCommutable = 1 in {
+  let isCommutable = 1 in {
     // Expands to LOCR or LOCFHR or a branch-and-move sequence,
     // depending on the choice of registers.
     def LOCRMux : CondBinaryRRFPseudo<GRX32, GRX32>;
     defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>;
   }
 
   // Load on condition.  Matched via DAG pattern.
   // Expands to LOC or LOCFH, depending on the choice of register.
   def LOCMux : CondUnaryRSYPseudo<nonvolatile_load, GRX32, 4>;
   defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, nonvolatile_load, GRH32, 4>;
 
   // Store on condition.  Expanded from CondStore* pseudos.
   // Expands to STOC or STOCFH, depending on the choice of register.
   def STOCMux : CondStoreRSYPseudo<GRX32, 4>;
   defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>;
 
   // Define AsmParser extended mnemonics for each general condition-code mask.
   foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",
                 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {
     def LOCHIAsm#V  : FixedCondBinaryRIE<CV<V>, "lochi",  0xEC42, GR32,
                                          imm32sx16>;
     def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64,
                                          imm64sx16>;
     def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32,
                                          imm32sx16>;
     def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>;
     def LOCFHAsm#V  : FixedCondUnaryRSY<CV<V>, "locfh",  0xEBE0, GRH32, 4>;
     def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>;
   }
 }
 
 let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in {
   // Move register on condition.  Expanded from Select* pseudos and
   // created by early if-conversion.
-  let hasSideEffects = 0, isCommutable = 1 in {
+  let isCommutable = 1 in {
     defm LOCR  : CondBinaryRRFPair<"locr",  0xB9F2, GR32, GR32>;
     defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>;
   }
 
   // Load on condition.  Matched via DAG pattern.
   defm LOC  : CondUnaryRSYPair<"loc",  0xEBF2, nonvolatile_load, GR32, 4>;
   defm LOCG : CondUnaryRSYPair<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
 
   // Store on condition.  Expanded from CondStore* pseudos.
   defm STOC  : CondStoreRSYPair<"stoc",  0xEBF3, GR32, 4>;
   defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>;
 
   // Define AsmParser extended mnemonics for each general condition-code mask.
   foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE",
                 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in {
     def LOCRAsm#V   : FixedCondBinaryRRF<CV<V>, "locr",  0xB9F2, GR32, GR32>;
     def LOCGRAsm#V  : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>;
     def LOCAsm#V    : FixedCondUnaryRSY<CV<V>, "loc",   0xEBF2, GR32, 4>;
     def LOCGAsm#V   : FixedCondUnaryRSY<CV<V>, "locg",  0xEBE2, GR64, 8>;
     def STOCAsm#V   : FixedCondStoreRSY<CV<V>, "stoc",  0xEBF3, GR32, 4>;
     def STOCGAsm#V  : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>;
   }
 }
 //===----------------------------------------------------------------------===//
 // Sign extensions
 //===----------------------------------------------------------------------===//
 //
 // Note that putting these before zero extensions mean that we will prefer
 // them for anyextload*.  There's not really much to choose between the two
 // either way, but signed-extending loads have a short LH and a long LHY,
 // while zero-extending loads have only the long LLH.
 //
 //===----------------------------------------------------------------------===//
 
 // 32-bit extensions from registers.
-let hasSideEffects = 0 in {
-  def LBR : UnaryRRE<"lbr", 0xB926, sext8,  GR32, GR32>;
-  def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>;
-}
 
 // 64-bit extensions from registers.
-let hasSideEffects = 0 in {
-  def LGBR : UnaryRRE<"lgbr", 0xB906, sext8,  GR64, GR64>;
-  def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>;
-  def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>;
-}
+
 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
   def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>;
 
 // Match 32-to-64-bit sign extensions in which the source is already
 // in a 64-bit register.
 def : Pat<(sext_inreg GR64:$src, i32),
           (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
 
 // 32-bit extensions from 8-bit memory.  LBMux expands to LB or LBH,
 // depending on the choice of register.
 def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
             Requires<[FeatureHighWord]>;
 def LB  : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;

 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
   def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
 
 //===----------------------------------------------------------------------===//
 // Zero extensions
 //===----------------------------------------------------------------------===//
 
 // 32-bit extensions from registers.
-let hasSideEffects = 0 in {
-  // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
-  def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>,
-                Requires<[FeatureHighWord]>;
-  def LLCR    : UnaryRRE<"llcr", 0xB994, zext8,  GR32, GR32>;
-  // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
-  def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>,
-                Requires<[FeatureHighWord]>;
-  def LLHR    : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;
-}
+
 
 // 64-bit extensions from registers.
-let hasSideEffects = 0 in {
-  def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8,  GR64, GR64>;
-  def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>;
-  def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>;
-}
 
 // Match 32-to-64-bit zero extensions in which the source is already
 // in a 64-bit register.
 def : Pat<(and GR64:$src, 0xffffffff),
           (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
 
 // 32-bit extensions from 8-bit memory.  LLCMux expands to LLC or LLCH,
 // depending on the choice of register.

 // Load and zero rightmost byte.
 let Predicates = [FeatureLoadAndZeroRightmostByte] in {
   def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>;
   def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00),
             (LLZRGF bdxaddr20only:$src)>;
 }
 
 // Load and trap.
-let Predicates = [FeatureLoadAndTrap] in {
+let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {
   def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>;
   def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>;
 }
 
 // Extend GR64s to GR128s.
 let usesCustomInserter = 1 in
   def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
 
 //===----------------------------------------------------------------------===//
 // "Any" extensions
 //===----------------------------------------------------------------------===//
 
 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
 def : Pat<(i64 (anyext GR32:$src)),
           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
 
 // Extend GR64s to GR128s.
 let usesCustomInserter = 1 in
   def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
 
 //===----------------------------------------------------------------------===//
 // Truncations
 //===----------------------------------------------------------------------===//
 
 // Truncations of 64-bit registers to 32-bit registers.
 def : Pat<(i32 (trunc GR64:$src)),

 defm : StoreGR64Pair<STC, STCY, truncstorei8>;
 defm : StoreGR64Pair<STH, STHY, truncstorei16>;
 def  : StoreGR64PC<STHRL, aligned_truncstorei16>;
 defm : StoreGR64Pair<ST, STY, truncstorei32>;
 def  : StoreGR64PC<STRL, aligned_truncstorei32>;
 
 // Store characters under mask -- not (yet) used for codegen.
 defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>;
 def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>;
 
 //===----------------------------------------------------------------------===//
 // Multi-register moves
 //===----------------------------------------------------------------------===//
 
 // Multi-register loads.
 defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>;
 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
 def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>;
 def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>;
 
 // Multi-register stores.
 defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>;
 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
 def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>;
 
 //===----------------------------------------------------------------------===//
 // Byte swaps
 //===----------------------------------------------------------------------===//
 
 // Byte-swapping register moves.
-let hasSideEffects = 0 in {
-  def LRVR  : UnaryRRE<"lrvr",  0xB91F, bswap, GR32, GR32>;
-  def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>;
-}
 
 // Byte-swapping loads.  Unlike normal loads, these instructions are
 // allowed to access storage more than once.
 def LRVH : UnaryRXY<"lrvh", 0xE31F, z_lrvh, GR32, 2>;
 def LRV  : UnaryRXY<"lrv",  0xE31E, z_lrv,  GR32, 4>;
 def LRVG : UnaryRXY<"lrvg", 0xE30F, z_lrvg, GR64, 8>;
 
 // Likewise byte-swapping stores.
 def STRVH : StoreRXY<"strvh", 0xE33F, z_strvh, GR32, 2>;
 def STRV  : StoreRXY<"strv",  0xE33E, z_strv,  GR32, 4>;
 def STRVG : StoreRXY<"strvg", 0xE32F, z_strvg, GR64, 8>;
 
 // Byte-swapping memory-to-memory moves.
 let mayLoad = 1, mayStore = 1 in
   def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>;
 
 //===----------------------------------------------------------------------===//
 // Load address instructions
 //===----------------------------------------------------------------------===//
 
 // Load BDX-style addresses.
-let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1 in
+let isAsCheapAsAMove = 1, isReMaterializable = 1 in
   defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>;
 
 // Load a PC-relative address.  There's no version of this instruction
 // with a 16-bit offset, so there's no relaxation.
-let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
-    isReMaterializable = 1 in
+let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in
   def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>;
 
 // Load the Global Offset Table address.  This will be lowered into a
 //     larl $R1, _GLOBAL_OFFSET_TABLE_
 // instruction.
 def GOT : Alias<6, (outs GR64:$R1), (ins),
                 [(set GR64:$R1, (global_offset_table))]>;
 

 
 defm : InsertMem<"inserti8", IC32,  GR32, azextloadi8, bdxaddr12pair>;
 defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
 
 defm : InsertMem<"inserti8", IC,  GR64, azextloadi8, bdxaddr12pair>;
 defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
 
 // Insert characters under mask -- not (yet) used for codegen.
 let Defs = [CC] in {
   defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>;
   def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>;
 }
 
 // Insertions of a 16-bit immediate, leaving other bits unaffected.
 // We don't have or_as_insert equivalents of these operations because
 // OI is available instead.
 //
let isCommutable = 1 in {
     defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, add, GR64, GR64>;
   }
   def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>;
 
   // Addition to a high register.
   def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>,
               Requires<[FeatureHighWord]>;
   def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>,
               Requires<[FeatureHighWord]>;
 
   // Addition of signed 16-bit immediates.
   defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>;
   defm AHI  : BinaryRIAndK<"ahi",  0xA7A, 0xECD8, add, GR32, imm32sx16>;
   defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
 
   // Addition of signed 32-bit immediates.
   def AFIMux : BinaryRIPseudo<add, GRX32, simm32>,
                Requires<[FeatureHighWord]>;
   def AFI  : BinaryRIL<"afi",  0xC29, add, GR32, simm32>;
   def AIH  : BinaryRIL<"aih",  0xCC8, add, GRH32, simm32>,
              Requires<[FeatureHighWord]>;
   def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
 
   // Addition of memory.
   defm AH  : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
   defm A   : BinaryRXPair<"a",  0x5A, 0xE35A, add, GR32, load, 4>;
   def  AGH : BinaryRXY<"agh", 0xE338, add, GR64, asextloadi16, 2>,
              Requires<[FeatureMiscellaneousExtensions2]>;
   def  AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
   def  AG  : BinaryRXY<"ag",  0xE308, add, GR64, load, 8>;
 
   // Addition to memory.
   def ASI  : BinarySIY<"asi",  0xEB6A, add, imm32sx8>;
   def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
 }
 defm : SXB<add, GR64, AGFR>;
 
 // Addition producing a carry.
 let Defs = [CC] in {
   // Addition of a register.
   let isCommutable = 1 in {
     defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, addc, GR32, GR32>;
let Defs = [CC] in {
   defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, subc, GR32, GR32>;
   def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>;
   defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, subc, GR64, GR64>;
 
   // Subtraction from a high register.
   def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>,
                Requires<[FeatureHighWord]>;
   def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>,
                Requires<[FeatureHighWord]>;
 
   // Subtraction of unsigned 32-bit immediates.  These don't match
   // subc because we prefer addc for constants.
   def SLFI  : BinaryRIL<"slfi",  0xC25, null_frag, GR32, uimm32>;
   def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
 
   // Subtraction of memory.
   defm SL   : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
   def  SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
   def  SLG  : BinaryRXY<"slg",  0xE30B, subc, GR64, load, 8>;
 }
 defm : ZXB<subc, GR64, SLGFR>;

 defm MS   : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
 def  MGH  : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>,
             Requires<[FeatureMiscellaneousExtensions2]>;
 def  MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
 def  MSG  : BinaryRXY<"msg",  0xE30C, mul, GR64, load, 8>;
 
 // Multiplication of memory, setting the condition code.
 let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in {
   def MSC  : BinaryRXY<"msc",  0xE353, null_frag, GR32, load, 4>;
   def MSGC : BinaryRXY<"msgc", 0xE383, null_frag, GR64, load, 8>;
 }
 
 // Multiplication of a register, producing two results.
 def MR   : BinaryRR <"mr",    0x1C,   null_frag, GR128, GR32>;
 def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>,
            Requires<[FeatureMiscellaneousExtensions2]>;
 def MLR  : BinaryRRE<"mlr",  0xB996, null_frag, GR128, GR32>;
 def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>;
+
 def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2),
           (MGRK GR64:$src1, GR64:$src2)>;
 def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2),
           (MLGR (AEXT128 GR64:$src1), GR64:$src2)>;
 
 // Multiplication of memory, producing two results.
 def M   : BinaryRX <"m",   0x5C,   null_frag, GR128, load, 4>;
 def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>;
 def MG  : BinaryRXY<"mg",  0xE384, null_frag, GR128, load, 8>,
           Requires<[FeatureMiscellaneousExtensions2]>;
 def ML  : BinaryRXY<"ml",  0xE396, null_frag, GR128, load, 4>;
 def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>;
+
 def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))),
           (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
 def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))),
           (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
 
 //===----------------------------------------------------------------------===//
 // Division and remainder
 //===----------------------------------------------------------------------===//

 def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))),
           (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>;
 
 //===----------------------------------------------------------------------===//
 // Shifts
 //===----------------------------------------------------------------------===//
 
 // Logical shift left.
-let hasSideEffects = 0 in {
-  defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
-  def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>;
-  def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>;
-}
 
 // Arithmetic shift left.
 let Defs = [CC] in {
   defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>;
   def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>;
   def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>;
 }
 
 // Logical shift right.
-let hasSideEffects = 0 in {
-  defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
-  def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>;
-  def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>;
-}
 
 // Arithmetic shift right.
 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
   defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
   def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>;
   def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>;
 }
 
 // Rotate left.
-let hasSideEffects = 0 in {
-  def RLL  : BinaryRSY<"rll",  0xEB1D, rotl, GR32>;
-  def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>;
-}
 
 // Rotate second operand left and inserted selected bits into first operand.
 // These can act like 32-bit operands provided that the constant start and
 // end bits (operands 2 and 3) are in the range [32, 64).
 let Defs = [CC] in {
   let isCodeGenOnly = 1 in
     def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
   let CCValues = 0xE, CompareZeroCCMask = 0xE in
let Defs = [CC], CCValues = 0xE in {
   def CR   : CompareRR <"cr",   0x19,   z_scmp,    GR32, GR32>;
   def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>;
   def CGR  : CompareRRE<"cgr",  0xB920, z_scmp,    GR64, GR64>;
 
   // Comparison with a high register.
   def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>,
              Requires<[FeatureHighWord]>;
   def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>,
              Requires<[FeatureHighWord]>;
 
   // Comparison with a signed 16-bit immediate.  CHIMux expands to CHI or CIH,
   // depending on the choice of register.
   def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>,
                Requires<[FeatureHighWord]>;
   def CHI  : CompareRI<"chi",  0xA7E, z_scmp, GR32, imm32sx16>;
   def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
 
let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
   def CLR   : CompareRR <"clr",   0x15,   z_ucmp,    GR32, GR32>;
   def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>;
   def CLGR  : CompareRRE<"clgr",  0xB921, z_ucmp,    GR64, GR64>;
 
   // Comparison with a high register.
   def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>,
               Requires<[FeatureHighWord]>;
   def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>,
               Requires<[FeatureHighWord]>;
 
   // Comparison with an unsigned 32-bit immediate.  CLFIMux expands to CLFI
   // or CLIH, depending on the choice of register.
   def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>,
                 Requires<[FeatureHighWord]>;
   def CLFI  : CompareRIL<"clfi",  0xC2F, z_ucmp, GR32, uimm32>;
   def CLIH  : CompareRIL<"clih",  0xCCF, z_ucmp, GRH32, uimm32>,
               Requires<[FeatureHighWord]>;
let Defs = [CC] in {
 
   defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
 }
 
 def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>;
 def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>;
 
 // Compare logical characters under mask -- not (yet) used for codegen.
 let Defs = [CC] in {
   defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>;
   def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>;
 }
 
 //===----------------------------------------------------------------------===//
 // Prefetch and execution hint
 //===----------------------------------------------------------------------===//
 
+let mayLoad = 1, mayStore = 1 in {
   def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
   def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
+}
 
-let Predicates = [FeatureExecutionHint] in {
+let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in {
   // Branch Prediction Preload
   def BPP : BranchPreloadSMI<"bpp", 0xC7>;
   def BPRP : BranchPreloadMII<"bprp", 0xC5>;
 
   // Next Instruction Access Intent
   def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>;
 }
 

 // A pseudo instruction that serves as a compiler barrier.
 let hasSideEffects = 1, hasNoSchedulingInfo = 1 in
 def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>;
 
 let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
   def LAA   : LoadAndOpRSY<"laa",   0xEBF8, atomic_load_add_32, GR32>;
   def LAAG  : LoadAndOpRSY<"laag",  0xEBE8, atomic_load_add_64, GR64>;
   def LAAL  : LoadAndOpRSY<"laal",  0xEBFA, null_frag, GR32>;
   def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>;
   def LAN   : LoadAndOpRSY<"lan",   0xEBF4, atomic_load_and_32, GR32>;
   def LANG  : LoadAndOpRSY<"lang",  0xEBE4, atomic_load_and_64, GR64>;
   def LAO   : LoadAndOpRSY<"lao",   0xEBF6, atomic_load_or_32, GR32>;
   def LAOG  : LoadAndOpRSY<"laog",  0xEBE6, atomic_load_or_64, GR64>;
   def LAX   : LoadAndOpRSY<"lax",   0xEBF7, atomic_load_xor_32, GR32>;
   def LAXG  : LoadAndOpRSY<"laxg",  0xEBE7, atomic_load_xor_64, GR64>;
 }
 
def ATOMIC_CMP_SWAPW
   let Defs = [CC];
   let mayLoad = 1;
   let mayStore = 1;
   let usesCustomInserter = 1;
   let hasNoSchedulingInfo = 1;
 }
 
 // Test and set.
 let mayLoad = 1, Defs = [CC] in
   def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>;
 
 // Compare and swap.
 let Defs = [CC] in {
   defm CS  : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>;
   def  CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>;
 }
 

 let mayLoad = 1, Defs = [CC, R0L, R1D] in {
   def TRT  : SideEffectBinarySSa<"trt", 0xDD>;
   def TRTR : SideEffectBinarySSa<"trtr", 0xD0>;
 }
 
 let mayLoad = 1, mayStore = 1, Uses = [R0L] in
   def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>;
 
 let mayLoad = 1, Uses = [R1D], Defs = [CC] in {
   defm TRTE  : BinaryMemRRFcOpt<"trte",  0xB9BF, GR128, GR64>;
   defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>;
 }
 
 let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in {
   defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>;
   defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>;
   defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>;
let Predicates = [FeatureMessageSecurityAssist8] in
     def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929,
                                               GR128, GR128, GR128>;
 }
 
 //===----------------------------------------------------------------------===//
 // Guarded storage
 //===----------------------------------------------------------------------===//
 
-let Predicates = [FeatureGuardedStorage] in {
+// These instructions use and/or modify the guarded storage control
+// registers, which we do not otherwise model, so they should have
+// hasSideEffects.
+let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in {
   def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>;
   def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>;
 
   let mayLoad = 1 in
     def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>;
   let mayStore = 1 in
     def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>;
 }
 
 //===----------------------------------------------------------------------===//
 // Decimal arithmetic
 //===----------------------------------------------------------------------===//
 
 defm CVB  : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>;
 def  CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>;
 
 defm CVD  : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>;
 def  CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>;
 
 let mayLoad = 1, mayStore = 1 in {
   def MVN : SideEffectBinarySSa<"mvn", 0xD1>;
   def MVZ : SideEffectBinarySSa<"mvz", 0xD3>;
   def MVO : SideEffectBinarySSb<"mvo", 0xF1>;
let mayLoad = 1, mayStore = 1 in {
   def MP : SideEffectBinarySSb<"mp", 0xFC>;
   def DP : SideEffectBinarySSb<"dp", 0xFD>;
   let Defs = [CC] in {
     def ED : SideEffectBinarySSa<"ed", 0xDE>;
     def EDMK : SideEffectBinarySSa<"edmk", 0xDF>;
   }
 }
 
 let Defs = [CC] in {
   def CP : CompareSSb<"cp", 0xF9>;
   def TP : TestRSL<"tp", 0xEBC0>;
 }
 
 //===----------------------------------------------------------------------===//
 // Access registers
 //===----------------------------------------------------------------------===//
 
 // Read a 32-bit access register into a GR32.  As with all GR32 operations,
 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
 // when a 64-bit address is stored in a pair of access registers.
 def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>;
 
 // Set access register.
 def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>;
 
 // Copy access register.
 def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>;
 
 // Load address extended.
 defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>;
 
 // Load access multiple.
 defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>;
 
-// Load access multiple.
+// Store access multiple.
 defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>;
 
 //===----------------------------------------------------------------------===//
 // Program mask and addressing mode
 //===----------------------------------------------------------------------===//
 
 // Extract CC and program mask into a register.  CC ends up in bits 29 and 28.
 let Uses = [CC] in
   def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>;
 
 // Set CC and program mask from a register.
 let hasSideEffects = 1, Defs = [CC] in
   def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>;
 
 // Branch and link - like BAS, but also extracts CC and program mask.
 let isCall = 1, Uses = [CC], Defs = [CC] in {
   def BAL  : CallRX<"bal", 0x45>;
   def BALR : CallRR<"balr", 0x05>;
 }
 
 // Test addressing mode.
 let Defs = [CC] in
   def TAM : SideEffectInherentE<"tam", 0x010B>;
 

 // Transactional execution
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in {
   // Transaction Begin
   let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in {
     def TBEGIN : SideEffectBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>;
     def TBEGIN_nofloat : SideEffectBinarySILPseudo<z_tbegin_nofloat, imm32zx16>;
-
     def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561,
                                       int_s390_tbeginc, imm32zx16>;
   }
 
   // Transaction End
   let Defs = [CC] in
     def TEND : SideEffectInherentS<"tend", 0xB2F8, z_tend>;
 
   // Transaction Abort
-  let isTerminator = 1, isBarrier = 1 in
+  // TODO: Shouldn't be mayLoad or mayStore.
+  let isTerminator = 1, isBarrier = 1, mayLoad = 1, mayStore = 1,
+      hasSideEffects = 1 in
     def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>;
 
   // Nontransactional Store
   def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
 
   // Extract Transaction Nesting Depth
   def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>;
 }
 
 //===----------------------------------------------------------------------===//
 // Processor assist
 //===----------------------------------------------------------------------===//

 //===----------------------------------------------------------------------===//
 // Miscellaneous Instructions.
 //===----------------------------------------------------------------------===//
 
 // Find leftmost one, AKA count leading zeros.  The instruction actually
 // returns a pair of GR64s, the first giving the number of leading zeros
 // and the second giving a copy of the source with the leftmost one bit
 // cleared.  We only use the first result here.
 let Defs = [CC] in
   def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>;
 def : Pat<(ctlz GR64:$src),
           (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
 
 // Population count.  Counts bits set per byte.
 let Predicates = [FeaturePopulationCount], Defs = [CC] in
   def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>;
 
let hasSideEffects = 1 in {
   def EX   : SideEffectBinaryRX<"ex", 0x44, GR64>;
   def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>;
 }
 
 //===----------------------------------------------------------------------===//
 // .insn directive instructions
 //===----------------------------------------------------------------------===//
 
-let isCodeGenOnly = 1 in {
+let isCodeGenOnly = 1, hasSideEffects = 1 in {
   def InsnE   : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>;
   def InsnRI  : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1,
                                              imm32sx16:$I2),
                                 ".insn ri,$enc,$R1,$I2", []>;
   def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1,
                                               AnyReg:$R3, brtarget16:$I2),
                                  ".insn rie,$enc,$R1,$R3,$I2", []>;
   def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1,

lib/Target/SystemZ/SystemZInstrSystem.td

 // Program-Status Word Instructions.
 //===----------------------------------------------------------------------===//
 
 // Extract PSW.
 let hasSideEffects = 1, Uses = [CC] in
   def EPSW : InherentDualRRE<"epsw", 0xB98D, GR32>;
 
 // Load PSW (extended).
-let hasSideEffects = 1, Defs = [CC], mayLoad = 1 in {
+let hasSideEffects = 1, Defs = [CC] in {
   def LPSW : SideEffectUnaryS<"lpsw", 0x8200, null_frag, 8>;
   def LPSWE : SideEffectUnaryS<"lpswe", 0xB2B2, null_frag, 16>;
 }
 
 // Insert PSW key.
 let Uses = [R2L], Defs = [R2L] in
   def IPK : SideEffectInherentS<"ipk", 0xB20B, null_frag>;
 
 // Set PSW key from address.
 let hasSideEffects = 1 in
   def SPKA : SideEffectAddressS<"spka", 0xB20A, null_frag>;
 
 // Set system mask.
-let hasSideEffects = 1, mayLoad = 1 in
+let hasSideEffects = 1 in
   def SSM : SideEffectUnaryS<"ssm", 0x8000, null_frag, 1>;
 
 // Store then AND/OR system mask.
 let hasSideEffects = 1 in {
   def STNSM : StoreSI<"stnsm", 0xAC, null_frag, imm32zx8>;
   def STOSM : StoreSI<"stosm", 0xAD, null_frag, imm32zx8>;
 }
 
 // Insert address space control.
 let hasSideEffects = 1 in
   def IAC : InherentRRE<"iac", 0xB224, GR32, null_frag>;
 
 // Set address space control (fast).
 let hasSideEffects = 1 in {
   def SAC : SideEffectAddressS<"sac", 0xB219, null_frag>;
   def SACF : SideEffectAddressS<"sacf", 0xB279, null_frag>;
 }
 
 //===----------------------------------------------------------------------===//
 // Control Register Instructions.
 //===----------------------------------------------------------------------===//
 
+let hasSideEffects = 1 in {
   // Load control.
   def LCTL : LoadMultipleRS<"lctl", 0xB7, CR64>;
   def LCTLG : LoadMultipleRSY<"lctlg", 0xEB2F, CR64>;
 
   // Store control.
   def STCTL : StoreMultipleRS<"stctl", 0xB6, CR64>;
   def STCTG : StoreMultipleRSY<"stctg", 0xEB25, CR64>;
+}
 
 // Extract primary ASN (and instance).
 let hasSideEffects = 1 in {
   def EPAR : InherentRRE<"epar", 0xB226, GR32, null_frag>;
   def EPAIR : InherentRRE<"epair", 0xB99A, GR64, null_frag>;
 }
 
 // Extract secondary ASN (and instance).

 
 // Load real address.
 let hasSideEffects = 1, Defs = [CC] in {
   defm LRA : LoadAddressRXPair<"lra", 0xB1, 0xE313, null_frag>;
   def LRAG : LoadAddressRXY<"lrag", 0xE303, null_frag, laaddr20pair>;
 }
 
 // Store real address.
 def STRAG : StoreSSE<"strag", 0xE502>;
 
 // Load using real address.
 let mayLoad = 1 in {
  def LURA : UnaryRRE<"lura", 0xB24B, null_frag, GR32, GR64>;
  def LURAG : UnaryRRE<"lurag", 0xB905, null_frag, GR64, GR64>;
 }
 
 // Store using real address.

lib/Target/SystemZ/SystemZInstrVector.td

 // Move instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [FeatureVector] in {
   // Register move.
   def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>;
   def VLR32 : UnaryAliasVRR<null_frag, v32sb, v32sb>;
   def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>;
 
   // Load GR from VR element.
   def VLGV  : BinaryVRScGeneric<"vlgv", 0xE721>;
   def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>;
   def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>;
   def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>;
   def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>;
 
   // Load VR element from GR.

 def : VectorExtractSubreg<v8i16, VLGVH>;
 def : VectorExtractSubreg<v4i32, VLGVF>;
 
 //===----------------------------------------------------------------------===//
 // Immediate instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [FeatureVector] in {
-  let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
-      isReMaterializable = 1 in {
+  let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
 
     // Generate byte mask.
     def VZERO : InherentVRIa<"vzero", 0xE744, 0>;
     def VONE  : InherentVRIa<"vone", 0xE744, 0xffff>;
     def VGBM  : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>;
 
     // Generate mask.
     def VGM  : BinaryVRIbGeneric<"vgm", 0xE746>;
def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)),
             (VLREPF bdxaddr12only:$addr)>;
   def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)),
             (VLREPG bdxaddr12only:$addr)>;
 
   // Use VLREP to load subvectors.  These patterns use "12pair" because
   // LEY and LDY offer full 20-bit displacement fields.  It's often better
   // to use those instructions rather than force a 20-bit displacement
   // into a GPR temporary.
+  let mayLoad = 1 in {
     def VL32 : UnaryAliasVRX<load, v32sb, bdxaddr12pair>;
     def VL64 : UnaryAliasVRX<load, v64db, bdxaddr12pair>;
+  }
 
   // Load logical element and zero.
   def VLLEZ  : UnaryVRXGeneric<"vllez", 0xE704>;
   def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8,  v128b, 1, 0>;
   def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>;
   def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>;
   def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>;
   def : Pat<(v4f32 (z_vllezf32 bdxaddr12only:$addr)),

 // Stores
 //===----------------------------------------------------------------------===//
 
 let Predicates = [FeatureVector] in {
   // Store.
   def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>;
 
   // Store with length.  The number of stored bytes is only known at run time.
   def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>;
 
   // Store multiple.
   def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>;
 
   // Store element.
   def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8,  v128b, 1, imm32zx4>;
   def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>;
   def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>;
   def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>;
   def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
                        imm32zx2:$index),
             (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
   def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,
                        imm32zx1:$index),
             (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
 
   // Use VSTE to store subvectors.  These patterns use "12pair" because
   // STEY and STDY offer full 20-bit displacement fields.  It's often better
   // to use those instructions rather than force a 20-bit displacement
   // into a GPR temporary.
+  let mayStore = 1 in {
     def VST32 : StoreAliasVRX<store, v32sb, bdxaddr12pair>;
     def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>;
+  }
 
   // Scatter element.
   def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>;
   def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>;
 }
 
 let Predicates = [FeatureVectorPackedDecimal] in {
   // Store rightmost with length.  The number of stored bytes is only known
   // at run time.
   def VSTRL : StoreLengthVSI<"vstrl", 0xE63D, int_s390_vstrl, 0>;
   def VSTRLR : StoreLengthVRSd<"vstrlr", 0xE63F, int_s390_vstrl, 0>;
 }
 
 //===----------------------------------------------------------------------===//
 // Selects and permutes

test/CodeGen/SystemZ/backchain.ll

 ; check that alloca copies the backchain
 define void @f4(i32 %len) "backchain" {
 ; CHECK-LABEL: f4:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: lgr %r1, %r15
 ; CHECK: aghi %r15, -160
 ; CHECK: stg %r1, 0(%r15)
 ; CHECK: lgr %r11, %r15
-; CHECK: lg [[BC:%r[0-9]+]], 0(%r15)
-; CHECK: lgr [[NEWSP:%r[0-9]+]], %r15
+; CHECK-DAG: lg [[BC:%r[0-9]+]], 0(%r15)
+; CHECK-DAG: lgr [[NEWSP:%r[0-9]+]], %r15
 ; CHECK: lgr %r15, [[NEWSP]]
 ; CHECK: stg [[BC]], 0([[NEWSP]])
   %ign = alloca i8, i32 %len
   ret void
 }
 
 ; check that llvm.stackrestore restores the backchain
 define void @f5(i32 %count1, i32 %count2) "backchain" {

test/CodeGen/SystemZ/risbg-01.ll

; CHECK: br %r14
   %shr = ashr i64 %foo, 60
   %and = and i64 %shr, 30
   ret i64 %and
 }
 
 ; Now try an arithmetic right shift in which the sign bits aren't needed.
 ; Introduce a second use of %shr so that the ashr doesn't decompose to
 ; an lshr.
+; NOTE: the extra move to %r2 should not be needed (temporary FAIL)
 define i32 @f21(i32 %foo, i32 *%dest) {
 ; CHECK-LABEL: f21:
-; CHECK: risbg %r2, %r2, 60, 190, 36
+; CHECK: risbg %r0, %r2, 60, 190, 36
+; CHECK: lr %r2, %r0
 ; CHECK: br %r14
   %shr = ashr i32 %foo, 28
   store i32 %shr, i32 *%dest
   %and = and i32 %shr, 14
   ret i32 %and
 }
 
 ; ...and again with i64.

test/CodeGen/SystemZ/twoaddr-sink.ll

+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-integrated-as
+;
+; Check that TwoAddressInstructionPass does not crash after sinking (and
+; revisiting) an instruction that was lowered by TII->convertToThreeAddress()
+; which contains a %noreg operand.
+
+define i32 @f23(i32 %old) {
+  %and1 = and i32 %old, 14
+  %and2 = and i32 %old, 254
+  %res1 = call i32 asm "stepa $1, $2, $3", "=h,r,r,0"(i32 %old, i32 %and1, i32 %and2)
+  %and3 = and i32 %res1, 127
+  %and4 = and i32 %res1, 128
+  %res2 = call i32 asm "stepb $1, $2, $3", "=r,h,h,0"(i32 %res1, i32 %and3, i32 %and4)
+  ret i32 %res2
+}

test/CodeGen/SystemZ/vec-trunc-to-i1.ll

-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
 ;
 ; Check that a widening truncate to a vector of i1 elements can be handled.
 
-
+; NOTE: REG2 is actually not needed (tempororary FAIL)
 define void @pr32275(<4 x i8> %B15) {
 ; CHECK-LABEL: pr32275:
 ; CHECK:       # BB#0: # %BB
-; CHECK-NEXT:    vrepif %v0, 1
-; CHECK-NEXT:  .LBB0_1: # %CF34
-; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vlgvb %r0, %v24, 3
+; CHECK-NEXT:    vrepif [[REG0:%v[0-9]]], 1
+; CHECK:         vlgvb %r0, %v24, 3
 ; CHECK-NEXT:    vlgvb %r1, %v24, 1
-; CHECK-NEXT:    vlvgp %v1, %r1, %r0
+; CHECK-NEXT:    vlvgp [[REG1:%v[0-9]]], %r1, %r0
 ; CHECK-NEXT:    vlgvb %r0, %v24, 0
-; CHECK-NEXT:    vlvgf %v1, %r0, 0
-; CHECK-NEXT:    vlgvb %r0, %v24, 2
-; CHECK-NEXT:    vlvgf %v1, %r0, 2
-; CHECK-NEXT:    vn %v1, %v1, %v0
-; CHECK-NEXT:    vlgvf %r0, %v1, 3
-; CHECK-NEXT:    tmll %r0, 1
+; CHECK-DAG:     vlr [[REG2:%v[0-9]]], [[REG1]]
+; CHECK-DAG:     vlvgf [[REG2]], %r0, 0
+; CHECK-DAG:     vlgvb [[REG3:%r[0-9]]], %v24, 2
+; CHECK-NEXT:    vlvgf [[REG2]], [[REG3]], 2
+; CHECK-NEXT:    vn [[REG2]], [[REG2]], [[REG0]]
+; CHECK-NEXT:    vlgvf [[REG4:%r[0-9]]], [[REG2]], 3
+; CHECK-NEXT:    tmll [[REG4]], 1
 ; CHECK-NEXT:    jne .LBB0_1
 ; CHECK-NEXT:  # BB#2: # %CF36
 ; CHECK-NEXT:    br %r14
 BB:
   br label %CF34
 
 CF34:
   %Tr24 = trunc <4 x i8> %B15 to <4 x i1>
   %E28 = extractelement <4 x i1> %Tr24, i32 3
   br i1 %E28, label %CF34, label %CF36
 
 CF36:
   ret void
 }