[mips] Use the delay slot filler to convert branches for microMIPSR6.

[sdardis]

Summary

The MIPS delay slot filler converts delay slot branches into compact
forms for the MIPS ISAs which support them. For branches that compare
(in)equality with with zero, it converts them into branches with implict
zero register operands. These branches have a slightly greater range
than normal two register operands branches.

Changing the branches at this point in the pipeline offers the long
branch pass the ability to mark better judgements if a long branch
sequence is required.

[atanasyan]

LGTM with the only nit.

test/CodeGen/Mips/llvm-ir/sub.ll

225 ↗

(On Diff #123818)

Does it make a sense to keep this line but replace jr by jrc?

[sdardis]

test/CodeGen/Mips/llvm-ir/sub.ll

225 ↗

(On Diff #123818)

I elected to remove it as it isn't really providing any value for the purposes of the test. None of the other test stanzas included any sort of end marker, so I removed it in this case.

[atanasyan]

test/CodeGen/Mips/llvm-ir/sub.ll

225 ↗

(On Diff #123818)

I see. ok

llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp

 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
 /// We assume there is only one delay slot per delayed instruction.
 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
   bool Changed = false;
   const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
   bool InMicroMipsMode = STI.inMicroMipsMode();
   const MipsInstrInfo *TII = STI.getInstrInfo();
 
-  if (InMicroMipsMode && STI.hasMips32r6()) {
-    // This is microMIPS32r6 or microMIPS64r6 processor. Delay slot for
-    // branching instructions is not needed.
-    return Changed;
-  }
-
   for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
     if (!hasUnoccupiedSlot(&*I))
       continue;
 
-    ++FilledSlots;
-    Changed = true;
+    // Delay slot filling is disabled at -O0, or in microMIPS32R6.
+    if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None) &&
+        !(InMicroMipsMode && STI.hasMips32r6())) {
 
-    // Delay slot filling is disabled at -O0.
-    if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None)) {
       bool Filled = false;
 
       if (MipsCompactBranchPolicy.getValue() != CB_Always ||
            !TII->getEquivalentCompactForm(I)) {
         if (searchBackward(MBB, *I)) {
           Filled = true;
         } else if (I->isTerminator()) {
           if (searchSuccBBs(MBB, I)) {
if (!DisableDelaySlotFiller && (TM->getOptLevel() != CodeGenOpt::None) &&
 
           // TODO: Implement an instruction mapping table of 16bit opcodes to
           // 32bit opcodes so that an instruction can be expanded. This would
           // save 16 bits as a TAILCALL_MM pseudo requires a fullsized nop.
           // TODO: Permit b16 when branching backwards to the the same function
           // if it is in range.
           DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
         }
+        ++FilledSlots;
+        Changed = true;
         continue;
       }
     }
 
     // For microMIPS if instruction is BEQ or BNE with one ZERO register, then
     // instead of adding NOP replace this instruction with the corresponding
     // compact branch instruction, i.e. BEQZC or BNEZC. Additionally
     // PseudoReturn and PseudoIndirectBranch are expanded to JR_MM, so they can
     // be replaced with JRC16_MM.
 
     // For MIPSR6 attempt to produce the corresponding compact (no delay slot)
     // form of the CTI. For indirect jumps this will not require inserting a
     // NOP and for branches will hopefully avoid requiring a NOP.
     if ((InMicroMipsMode ||
          (STI.hasMips32r6() && MipsCompactBranchPolicy != CB_Never)) &&
         TII->getEquivalentCompactForm(I)) {
       I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
+      Changed = true;
       continue;
     }
 
     // Bundle the NOP to the instruction with the delay slot.
     BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
     MIBundleBuilder(MBB, I, std::next(I, 2));
+    ++FilledSlots;
+    Changed = true;
   }
 
   return Changed;
 }
 
 template<typename IterTy>
 bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
                          RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot,

llvm/trunk/test/CodeGen/Mips/fcmp.ll

 ; MM32R3-DAG:    bc1t
 
 ; MM32R6-DAG:    add.s    $[[T0:f[0-9]+]], $f14, $f12
 ; MM32R6-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI32_0)
 ; MM32R6-DAG:    lwc1     $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
 ; MM32R6-DAG:    cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
 ; MM32R6-DAG:    mfc1     $[[T4:[0-9]+]], $[[T3:f[0-9]+]]
 ; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
-; MM32R6-DAG:    bnez     $[[T5]],
+; MM32R6-DAG:    bnezc    $[[T5]],
 
 ; MM64R6-DAG:    add.s    $[[T0:f[0-9]+]], $f13, $f12
 ; MM64R6-DAG:    lui      $[[T1:[0-9]+]], %highest(.LCPI32_0)
 ; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI32_0)
 ; MM64R6-DAG:    dsll     $[[T3:[0-9]+]], $[[T2]], 16
 ; MM64R6-DAG:    daddiu   $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI32_0)
 ; MM64R6-DAG:    dsll     $[[T5:[0-9]+]], $[[T4]], 16
 ; MM64R6-DAG:    lwc1     $[[T6:f[0-9]+]], %lo(.LCPI32_0)($[[T5]])
 ; MM64R6-DAG:    cmp.le.s $[[T7:f[0-9]+]], $[[T0]], $[[T6]]
 ; MM64R6-DAG:    mfc1     $[[T8:[0-9]+]], $[[T7]]
 ; MM64R6-DAG:    andi16   $[[T9:[0-9]+]], $[[T8]], 1
-; MM64R6-DAG:    bnez     $[[T9]],
+; MM64R6-DAG:    bnezc    $[[T9]],
 
   %add = fadd fast float %at, %angle
   %cmp = fcmp ogt float %add, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   %sub = fadd fast float %add, -1.000000e+00
   br label %if.end

 ; MM32R3-DAG:    bc1t
 
 ; MM32R6-DAG:    add.d    $[[T0:f[0-9]+]], $f14, $f12
 ; MM32R6-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI33_0)
 ; MM32R6-DAG:    ldc1     $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
 ; MM32R6-DAG:    cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
 ; MM32R6-DAG:    mfc1     $[[T4:[0-9]+]], $[[T3]]
 ; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
-; MM32R6-DAG:    bnez     $[[T5]],
+; MM32R6-DAG:    bnezc    $[[T5]],
 
 ; MM64R6-DAG:    add.d    $[[T0:f[0-9]+]], $f13, $f12
 ; MM64R6-DAG:    lui      $[[T1:[0-9]+]], %highest(.LCPI33_0)
 ; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI33_0)
 ; MM64R6-DAG:    dsll     $[[T3:[0-9]+]], $[[T2]], 16
 ; MM64R6-DAG:    daddiu   $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI33_0)
 ; MM64R6-DAG:    dsll     $[[T5:[0-9]+]], $[[T4]], 16
 ; MM64R6-DAG:    ldc1     $[[T6:f[0-9]+]], %lo(.LCPI33_0)($[[T5]])
 ; MM64R6-DAG:    cmp.le.d $[[T7:f[0-9]+]], $[[T0]], $[[T6]]
 ; MM64R6-DAG:    mfc1     $[[T8:[0-9]+]], $[[T7]]
 ; MM64R6-DAG:    andi16   $[[T9:[0-9]+]], $[[T8]], 1
-; MM64R6-DAG:    bnez     $[[T9]],
+; MM64R6-DAG:    bnezc    $[[T9]],
 
   %add = fadd fast double %at, %angle
   %cmp = fcmp ogt double %add, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:
   %sub = fadd fast double %add, -1.000000e+00
   br label %if.end
 
 if.end:
   %theta.0 = phi double [ %sub, %if.then ], [ %add, %entry ]
   ret double %theta.0
 }
 
 attributes #0 = { nounwind readnone "no-nans-fp-math"="true" }

llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll

 ;        dext instruction which should be used here.
 
 ; MM64: dsubu   $[[T0:[0-9]+]], $4, $6
 ; MM64: sltu    $[[T1:[0-9]+]], $5, $7
 ; MM64: dsll    $[[T2:[0-9]+]], $[[T1]], 32
 ; MM64: dsrl    $[[T3:[0-9]+]], $[[T2]], 32
 ; MM64: dsubu   $2, $[[T0]], $[[T3]]
 ; MM64: dsubu   $3, $5, $7
-; MM64: jr      $ra
 
   %r = sub i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/tailcall/tailcall.ll

 ; ALL-LABEL: caller8_0:
 ; PIC32: jr $25
 ; PIC32R6: jrc $25
 ; PIC32MM: jrc
 ; STATIC32: j
 ; STATIC32MMR6: bc
 ; PIC64: jr $25
 ; PIC64R6: jrc $25
-; PIC64R6MM: jr $25
+; PIC64R6MM: jrc $25
 ; STATIC64: j
 ; PIC16: jalrc
 
   %call = tail call fastcc i32 @caller8_1()
   ret i32 %call
 }
 
 define internal fastcc i32 @caller8_1() nounwind noinline {