[RISCV 11.5/n] Codegen support for materializing constants

[asb]

Summary

Splitting out support for materializing constants, as suggested by @reames in D29934.

This patch adds support and tests for materializing 32-bit constants.

[sdardis]

lib/Target/RISCV/RISCVInstrInfo.td

281 ↗

(On Diff #119600)

You should add the LUI pattern for materializing constants where the lower 12 bits are all zeros,

[asb]

lib/Target/RISCV/RISCVInstrInfo.td

281 ↗

(On Diff #119600)

Agreed, thanks for the comment. I had someone who has been playing with this patchset do this and send me a patch + tests via email. In order to track code ownership properly (and get them introduced to the LLVM code review process), they will submit to phabricator. It would probably make sense to commit this patch with a // TODO: add pattern for immediate with lower 12 bits all zeros.

[sdardis]

lib/Target/RISCV/RISCVInstrInfo.td

281 ↗

(On Diff #119600)

In order to track code ownership properly (and get them introduced to the LLVM code review process), they will submit to phabricator. It would probably make sense to commit this patch with a // TODO: add pattern for immediate with lower 12 bits all zeros.

Sounds reasonable.

[asb]

Split out the immediate materialisation tests to a separate file and add a TODO for immediates with lo12=0.

[reames]

LGTM

llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td

 
 // A 21-bit signed immediate where the least significant bit is zero.
 def simm21_lsb0 : Operand<XLenVT> {
   let ParserMatchClass = SImmAsmOperand<21, "Lsb0">;
   let EncoderMethod = "getImmOpValueAsr1";
   let DecoderMethod = "decodeSImmOperandAndLsl1<21>";
 }
 
+// Standalone (codegen-only) immleaf patterns.
+def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
+
+// Extract least significant 12 bits from an immediate value and sign extend
+// them.
+def LO12Sext : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(SignExtend64<12>(N->getZExtValue()),
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
+// Extract the most significant 20 bits from an immediate value. Add 1 if bit
+// 11 is 1, to compensate for the low 12 bits in the matching immediate addi
+// or ld/st being negative.
+def HI20 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(((N->getZExtValue()+0x800) >> 12) & 0xfffff,
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Class Templates
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class BranchCC_rri<bits<3> funct3, string opcodestr>
     : RVInstB<funct3, OPC_BRANCH, (outs),
               (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),

 class PatGprGpr<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
 class PatGprSimm12<SDPatternOperator OpNode, RVInstI Inst>
     : Pat<(OpNode GPR:$rs1, simm12:$imm12), (Inst GPR:$rs1, simm12:$imm12)>;
 class PatGprUimm5<SDPatternOperator OpNode, RVInstIShift Inst>
     : Pat<(OpNode GPR:$rs1, uimm5:$shamt),
           (Inst GPR:$rs1, uimm5:$shamt)>;
 
+/// Immediates
+
+def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>;
+// TODO: Add a pattern for immediates with all zeroes in the lower 12 bits.
+def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>;
+
 /// Simple arithmetic operations
 
 def : PatGprGpr<add, ADD>;
 def : PatGprSimm12<add, ADDI>;
 def : PatGprGpr<sub, SUB>;
 def : PatGprGpr<or, OR>;
 def : PatGprSimm12<or, ORI>;
 def : PatGprGpr<and, AND>;

llvm/trunk/test/CodeGen/RISCV/alu32.ll

 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 
 ; Register-immediate instructions
 
 define i32 @addi(i32 %a) nounwind {
 ; RV32I-LABEL: addi:
 ; RV32I: addi a0, a0, 1
 ; RV32I: jalr zero, ra, 0
-; TODO: check support for materialising larger constants
   %1 = add i32 %a, 1
   ret i32 %1
 }
 
 define i32 @slti(i32 %a) nounwind {
 ; RV32I-LABEL: slti:
 ; RV32I: slti a0, a0, 2
 ; RV32I: jalr zero, ra, 0

llvm/trunk/test/CodeGen/RISCV/imm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I
+
+; Materializing constants
+
+define i32 @zero() nounwind {
+; RV32I-LABEL: zero:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    addi a0, zero, 0
+; RV32I-NEXT:    jalr zero, ra, 0
+  ret i32 0
+}
+
+define i32 @pos_small() nounwind {
+; RV32I-LABEL: pos_small:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    addi a0, zero, 2047
+; RV32I-NEXT:    jalr zero, ra, 0
+  ret i32 2047
+}
+
+define i32 @neg_small() nounwind {
+; RV32I-LABEL: neg_small:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    addi a0, zero, -2048
+; RV32I-NEXT:    jalr zero, ra, 0
+  ret i32 -2048
+}
+
+define i32 @pos_i32() nounwind {
+; RV32I-LABEL: pos_i32:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    lui a0, 423811
+; RV32I-NEXT:    addi a0, a0, -1297
+; RV32I-NEXT:    jalr zero, ra, 0
+  ret i32 1735928559
+}
+
+define i32 @neg_i32() nounwind {
+; RV32I-LABEL: neg_i32:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    lui a0, 912092
+; RV32I-NEXT:    addi a0, a0, -273
+; RV32I-NEXT:    jalr zero, ra, 0
+  ret i32 -559038737
+}