[X86][F16C] Update instruction scheduling on btver2

[avt77]

Summary

This patch includes proper schedule numbers for F16C instructions on btver2 CPU.

[RKSimon]

lib/Target/X86/X86ScheduleBtVer2.td

427

I think 'ResourceCycles = [1];' is the default so you should be able to drop this?

435

Split off the cvtph2ps instructions from cvtps2ph - the load/store cases are definitely different and it makes little sense to keep the rr cases together.

437

Shouldn't the JFPU1 case be JFPU01? The amd docs say 'STC,FPA|FPM'

444

Shouldn't the JFPU1 case be JFPU01?

458

cvtph2ps is a load, so the JLAGU is the first stage not the last.

test/CodeGen/X86/f16c-schedule.ll

48

This should be [8:1.00]

106

These should be [8:2.00] and [3:2.00]?

[avt77]

lib/Target/X86/X86ScheduleBtVer2.td

437

It's again a difference between Agner and AMD docs :-(

[avt77]

I fixed issues raised by Simon

[RKSimon]

These latencies/throughputs still don't match the AMD docs - please match those and not the Agner tests

lib/Target/X86/X86ScheduleBtVer2.td

436

VCVTPH2PSrm is a load not a store it can't use WriteCVT3St

453

3

460

3 + 5 = 8

[avt77]

All numbers are from AMD docs now.

[RKSimon]

Rebase this?

[avt77]

I rebased f16c-schedule.ll.

[avt77]

I'm not shure about WriteCVT3St lattency: is it really 3?

[RKSimon]

In D39051#904742, @avt77 wrote:

I'm not shure about WriteCVT3St lattency: is it really 3?

Stores are tricky as we can't easily model the time until the value is written out to memory - best we can do is just the cycles for the conversion, and it then disappears into the memory queue. It means that spill/reload round trips can't be easily modelled but then we don't handle STLF timings either.

LGTM with one minor.

lib/Target/X86/X86ScheduleBtVer2.td

438

This should be Latency = 8

lib/Target/X86/X86ScheduleBtVer2.td

 
 def WriteINSERTQ: SchedWriteRes<[JFPU01]> {
   let Latency = 2;
   let ResourceCycles = [4];
 }
 def : InstRW<[WriteINSERTQ], (instregex "INSERTQ")>;
 
 ////////////////////////////////////////////////////////////////////////////////
+// F16C instructions.
+////////////////////////////////////////////////////////////////////////////////
+
+def WriteCVT3: SchedWriteRes<[JFPU1]> {
+  let Latency = 3;
+}
+def : InstRW<[WriteCVT3], (instregex "VCVTPS2PHrr")>;
+def : InstRW<[WriteCVT3], (instregex "VCVTPH2PSrr")>;
+
+def WriteCVT3St: SchedWriteRes<[JFPU1, JLAGU]> {
+  let Latency = 3;
+  let ResourceCycles = [1, 1];
+}
+def : InstRW<[WriteCVT3St], (instregex "VCVTPS2PHmr")>;
+
+def WriteCVT3Ld: SchedWriteRes<[JFPU1, JLAGU]> {
+  let Latency = 3;
+  let ResourceCycles = [1, 1];
+}
+def : InstRW<[WriteCVT3Ld], (instregex "VCVTPH2PSrm")>;
+
+def WriteCVTPS2PHY: SchedWriteRes<[JFPU1, JFPU01]> {
+  let Latency = 6;
+  let ResourceCycles = [2,2];
+  let NumMicroOps = 3;
+}
+def : InstRW<[WriteCVTPS2PHY], (instregex "VCVTPS2PHYrr")>;
+
+def WriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JFPU01, JLAGU]> {
+  let Latency = 11;
+  let ResourceCycles = [2,2,1];
+  let NumMicroOps = 3;
+}
+def : InstRW<[WriteCVTPS2PHYSt], (instregex "VCVTPS2PHYmr")>;
+
+def WriteCVTPH2PSY: SchedWriteRes<[JFPU1]> {
+  let Latency = 3;
+  let ResourceCycles = [2];
+  let NumMicroOps = 2;
+}
+def : InstRW<[WriteCVTPH2PSY], (instregex "VCVTPH2PSYrr")>;
+
+def WriteCVTPH2PSYLd: SchedWriteRes<[JLAGU, JFPU1]> {
+  let Latency = 8;
+  let ResourceCycles = [1,2];
+  let NumMicroOps = 2;
+}
+def : InstRW<[WriteCVTPH2PSYLd], (instregex "VCVTPH2PSYrm")>;
+
+////////////////////////////////////////////////////////////////////////////////
 // AVX instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 def WriteVDPPSY: SchedWriteRes<[JFPU1, JFPU0]> {
   let Latency = 12;
   let ResourceCycles = [6, 6];
   let NumMicroOps = 10;
 }

test/CodeGen/X86/f16c-schedule.ll

 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [9:0.50]
 ; SKYLAKE-NEXT:    vcvtph2ps %xmm0, %xmm0 # sched: [5:1.00]
 ; SKYLAKE-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    ret{{[l|q]}} # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_vcvtph2ps_128:
 ; BTVER2:       # BB#0:
-; BTVER2-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [8:1.00]
+; BTVER2-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [3:1.00]
 ; BTVER2-NEXT:    vcvtph2ps %xmm0, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    vaddps %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
 ; BTVER2-NEXT:    ret{{[l|q]}} # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_vcvtph2ps_128:
 ; ZNVER1:       # BB#0:
 ; ZNVER1-NEXT:    vcvtph2ps (%rdi), %xmm1 # sched: [100:?]
 ; ZNVER1-NEXT:    vcvtph2ps %xmm0, %xmm0 # sched: [100:?]

 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [10:0.50]
 ; SKYLAKE-NEXT:    vcvtph2ps %xmm0, %ymm0 # sched: [7:1.00]
 ; SKYLAKE-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [4:0.50]
 ; SKYLAKE-NEXT:    ret{{[l|q]}} # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_vcvtph2ps_256:
 ; BTVER2:       # BB#0:
-; BTVER2-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [8:1.00]
-; BTVER2-NEXT:    vcvtph2ps %xmm0, %ymm0 # sched: [3:1.00]
+; BTVER2-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [8:2.00]
+; BTVER2-NEXT:    vcvtph2ps %xmm0, %ymm0 # sched: [3:2.00]
 ; BTVER2-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:2.00]
 ; BTVER2-NEXT:    ret{{[l|q]}} # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_vcvtph2ps_256:
 ; ZNVER1:       # BB#0:
 ; ZNVER1-NEXT:    vcvtph2ps (%rdi), %ymm1 # sched: [100:?]
 ; ZNVER1-NEXT:    vcvtph2ps %xmm0, %ymm0 # sched: [100:?]
 ; ZNVER1-NEXT:    vaddps %ymm0, %ymm1, %ymm0 # sched: [3:1.00]

 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vcvtps2ph $0, %xmm0, %xmm0 # sched: [5:1.00]
 ; SKYLAKE-NEXT:    vcvtps2ph $0, %xmm1, (%rdi) # sched: [6:1.00]
 ; SKYLAKE-NEXT:    ret{{[l|q]}} # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_vcvtps2ph_128:
 ; BTVER2:       # BB#0:
 ; BTVER2-NEXT:    vcvtps2ph $0, %xmm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT:    vcvtps2ph $0, %xmm1, (%rdi) # sched: [8:1.00]
+; BTVER2-NEXT:    vcvtps2ph $0, %xmm1, (%rdi) # sched: [3:1.00]
 ; BTVER2-NEXT:    ret{{[l|q]}} # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_vcvtps2ph_128:
 ; ZNVER1:       # BB#0:
 ; ZNVER1-NEXT:    vcvtps2ph $0, %xmm0, %xmm0 # sched: [100:?]
 ; ZNVER1-NEXT:    vcvtps2ph $0, %xmm1, (%rdi) # sched: [100:?]
 ; ZNVER1-NEXT:    ret{{[l|q]}} # sched: [1:0.50]
   %1 = call <8 x i16> @llvm.x86.vcvtps2ph.128(<4 x float> %a0, i32 0)

 ; SKYLAKE:       # BB#0:
 ; SKYLAKE-NEXT:    vcvtps2ph $0, %ymm0, %xmm0 # sched: [7:1.00]
 ; SKYLAKE-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [8:1.00]
 ; SKYLAKE-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKYLAKE-NEXT:    ret{{[l|q]}} # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_vcvtps2ph_256:
 ; BTVER2:       # BB#0:
-; BTVER2-NEXT:    vcvtps2ph $0, %ymm0, %xmm0 # sched: [3:1.00]
-; BTVER2-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [8:1.00]
+; BTVER2-NEXT:    vcvtps2ph $0, %ymm0, %xmm0 # sched: [6:2.00]
+; BTVER2-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [11:2.00]
 ; BTVER2-NEXT:    ret{{[l|q]}} # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_vcvtps2ph_256:
 ; ZNVER1:       # BB#0:
 ; ZNVER1-NEXT:    vcvtps2ph $0, %ymm0, %xmm0 # sched: [100:?]
 ; ZNVER1-NEXT:    vcvtps2ph $0, %ymm1, (%rdi) # sched: [100:?]
 ; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
 ; ZNVER1-NEXT:    ret{{[l|q]}} # sched: [1:0.50]
   %1 = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a0, i32 0)
   %2 = call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %a1, i32 0)
   store <8 x i16> %2, <8 x i16> *%a2
   ret <8 x i16> %1
 }
 declare <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float>, i32)