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Differential D38274

[X86] Add support for v16i32 UMUL_LOHI/SMUL_LOHI
ClosedPublic

Authored by craig.topper on Sep 25 2017, 10:02 PM.

Details

Reviewers
zvi
RKSimon
Commits
rGf51913155c54: [X86] Add support for v16i32 UMUL_LOHI/SMUL_LOHI
rL314221: [X86] Add support for v16i32 UMUL_LOHI/SMUL_LOHI
Summary

This patch extends the v8i32/v4i32 custom lowering to support v16i32

Diff Detail

Event Timeline

craig.topper created this revision.Sep 25 2017, 10:02 PM
RKSimon accepted this revision.Sep 26 2017, 8:24 AM

LGTM

lib/Target/X86/X86ISelLowering.cpp
21849

clang-format this? The spacing looks off to me.

This revision is now accepted and ready to land.Sep 26 2017, 8:24 AM
Closed by commit rL314221: [X86] Add support for v16i32 UMUL_LOHI/SMUL_LOHI (authored by ctopper). · Explain WhySep 26 2017, 3:34 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
X86/
37 lines
test/
CodeGen/
X86/
404 lines
356 lines

Diff 116644

lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,292 Lines • ▼ Show 20 Lines if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
setOperationAction(ISD::MUL, MVT::v8i64, Custom); setOperationAction(ISD::MUL, MVT::v8i64, Custom);
setOperationAction(ISD::MUL, MVT::v16i32, Legal);
setOperationAction(ISD::UMUL_LOHI, MVT::v16i32, Custom);
setOperationAction(ISD::SMUL_LOHI, MVT::v16i32, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom); setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);
setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom); setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom); setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom);
setOperationAction(ISD::SELECT, MVT::v8f64, Custom); setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
setOperationAction(ISD::SELECT, MVT::v8i64, Custom); setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
setOperationAction(ISD::SELECT, MVT::v16f32, Custom); setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
setOperationAction(ISD::MUL, MVT::v16i32, Legal);
// NonVLX sub-targets extend 128/256 vectors to use the 512 version. // NonVLX sub-targets extend 128/256 vectors to use the 512 version.
setOperationAction(ISD::ABS, MVT::v4i64, Legal); setOperationAction(ISD::ABS, MVT::v4i64, Legal);
setOperationAction(ISD::ABS, MVT::v2i64, Legal); setOperationAction(ISD::ABS, MVT::v2i64, Legal);
for (auto VT : { MVT::v8i1, MVT::v16i1 }) { for (auto VT : { MVT::v8i1, MVT::v16i1 }) {
setOperationAction(ISD::ADD, VT, Custom); setOperationAction(ISD::ADD, VT, Custom);
setOperationAction(ISD::SUB, VT, Custom); setOperationAction(ISD::SUB, VT, Custom);
▲ Show 20 Lines • Show All 20,477 Lines • ▼ Show 20 Lines if (VT.is256BitVector() && !Subtarget.hasInt256()) {
SDValue Ops[] = { SDValue Ops[] = {
DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo.getValue(0), Hi.getValue(0)), DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo.getValue(0), Hi.getValue(0)),
DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo.getValue(1), Hi.getValue(1)) DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo.getValue(1), Hi.getValue(1))
}; };
return DAG.getMergeValues(Ops, dl); return DAG.getMergeValues(Ops, dl);
} }
assert((VT == MVT::v4i32 && Subtarget.hasSSE2()) || assert((VT == MVT::v4i32 && Subtarget.hasSSE2()) ||
(VT == MVT::v8i32 && Subtarget.hasInt256())); (VT == MVT::v8i32 && Subtarget.hasInt256()) ||
(VT == MVT::v16i32 && Subtarget.hasAVX512()));
int NumElts = VT.getVectorNumElements();
// PMULxD operations multiply each even value (starting at 0) of LHS with // PMULxD operations multiply each even value (starting at 0) of LHS with
// the related value of RHS and produce a widen result. // the related value of RHS and produce a widen result.
// E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h> // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
// => <2 x i64> <ae|cg> // => <2 x i64> <ae|cg>
// //
// In other word, to have all the results, we need to perform two PMULxD: // In other word, to have all the results, we need to perform two PMULxD:
// 1. one with the even values. // 1. one with the even values.
// 2. one with the odd values. // 2. one with the odd values.
// To achieve #2, with need to place the odd values at an even position. // To achieve #2, with need to place the odd values at an even position.
// //
// Place the odd value at an even position (basically, shift all values 1 // Place the odd value at an even position (basically, shift all values 1
// step to the left): // step to the left):
const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1}; const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1, 9, -1, 11, -1, 13, -1, 15, -1};
// <a|b|c|d> => <b|undef|d|undef> // <a|b|c|d> => <b|undef|d|undef>
SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0,
makeArrayRef(&Mask[0], VT.getVectorNumElements())); makeArrayRef(&Mask[0], NumElts));
// <e|f|g|h> => <f|undef|h|undef> // <e|f|g|h> => <f|undef|h|undef>
SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1,
makeArrayRef(&Mask[0], VT.getVectorNumElements())); makeArrayRef(&Mask[0], NumElts));
// Emit two multiplies, one for the lower 2 ints and one for the higher 2 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
// ints. // ints.
MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64; MVT MulVT = MVT::getVectorVT(MVT::i64, NumElts / 2);
bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI; bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
unsigned Opcode = unsigned Opcode =
(!IsSigned || !Subtarget.hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ; (!IsSigned || !Subtarget.hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
// PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h> // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
// => <2 x i64> <ae|cg> // => <2 x i64> <ae|cg>
SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1)); SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
// PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef> // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
// => <2 x i64> <bf|dh> // => <2 x i64> <bf|dh>
SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1)); SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
// Shuffle it back into the right order. // Shuffle it back into the right order.
SDValue Highs, Lows; SmallVector<int, 16> HighMask(NumElts);
if (VT == MVT::v8i32) { SmallVector<int, 16> LowMask(NumElts);
const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15}; for (int i = 0; i != NumElts; ++i) {
Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask); HighMask[i] = (i/2)*2 + ((i % 2) * NumElts) + 1;
const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14}; LowMask[i] = (i/2)*2 + ((i % 2) * NumElts);
RKSimonUnsubmitted
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clang-format this? The spacing looks off to me.

RKSimon: clang-format this? The spacing looks off to me.
Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
} else {
const int HighMask[] = {1, 5, 3, 7};
Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
const int LowMask[] = {0, 4, 2, 6};
Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
} }
SDValue Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
SDValue Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
// If we have a signed multiply but no PMULDQ fix up the high parts of a // If we have a signed multiply but no PMULDQ fix up the high parts of a
// unsigned multiply. // unsigned multiply.
if (IsSigned && !Subtarget.hasSSE41()) { if (IsSigned && !Subtarget.hasSSE41()) {
SDValue ShAmt = DAG.getConstant( SDValue ShAmt = DAG.getConstant(
31, dl, 31, dl,
DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout())); DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
SDValue T1 = DAG.getNode(ISD::AND, dl, VT, SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1); DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
▲ Show 20 Lines • Show All 15,246 Lines • Show Last 20 Lines

test/CodeGen/X86/vector-idiv-sdiv-512.ll

Show First 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; AVX-NEXT: retq ; AVX-NEXT: retq
%res = sdiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7> %res = sdiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res ret <8 x i64> %res
} }
define <16 x i32> @test_div7_16i32(<16 x i32> %a) nounwind { define <16 x i32> @test_div7_16i32(<16 x i32> %a) nounwind {
; AVX-LABEL: test_div7_16i32: ; AVX-LABEL: test_div7_16i32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; AVX-NEXT: vpbroadcastd {{.*#+}} zmm1 = [2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027]
; AVX-NEXT: vpextrd $1, %xmm1, %eax ; AVX-NEXT: vpmuldq %zmm1, %zmm0, %zmm2
; AVX-NEXT: cltq ; AVX-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493 ; AVX-NEXT: vpshufd {{.*#+}} zmm3 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: vpmuldq %zmm1, %zmm3, %zmm1
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: vmovdqa32 {{.*#+}} zmm3 = [1,17,3,19,5,21,7,23,9,25,11,27,13,29,15,31]
; AVX-NEXT: movl %eax, %ecx ; AVX-NEXT: vpermi2d %zmm1, %zmm2, %zmm3
; AVX-NEXT: shrl $31, %ecx ; AVX-NEXT: vpaddd %zmm0, %zmm3, %zmm0
; AVX-NEXT: sarl $2, %eax ; AVX-NEXT: vpsrld $31, %zmm0, %zmm1
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: vpsrad $2, %zmm0, %zmm0
; AVX-NEXT: vmovd %xmm1, %ecx ; AVX-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm2
; AVX-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $2, %xmm1, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $3, %xmm1, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm2, %xmm1
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vpextrd $1, %xmm0, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vmovd %xmm0, %ecx
; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm0, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm0, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: movl %eax, %ecx
; AVX-NEXT: shrl $31, %ecx
; AVX-NEXT: sarl $2, %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm0
; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%res = sdiv <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> %res = sdiv <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
ret <16 x i32> %res ret <16 x i32> %res
} }
define <32 x i16> @test_div7_32i16(<32 x i16> %a) nounwind { define <32 x i16> @test_div7_32i16(<32 x i16> %a) nounwind {
; AVX512F-LABEL: test_div7_32i16: ; AVX512F-LABEL: test_div7_32i16:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
▲ Show 20 Lines • Show All 893 Lines • ▼ Show 20 Lines
; AVX-NEXT: retq ; AVX-NEXT: retq
%res = srem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7> %res = srem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res ret <8 x i64> %res
} }
define <16 x i32> @test_rem7_16i32(<16 x i32> %a) nounwind { define <16 x i32> @test_rem7_16i32(<16 x i32> %a) nounwind {
; AVX-LABEL: test_rem7_16i32: ; AVX-LABEL: test_rem7_16i32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; AVX-NEXT: vpbroadcastd {{.*#+}} zmm1 = [2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027,2454267027]
; AVX-NEXT: vpextrd $1, %xmm1, %eax ; AVX-NEXT: vpmuldq %zmm1, %zmm0, %zmm2
; AVX-NEXT: cltq ; AVX-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493 ; AVX-NEXT: vpshufd {{.*#+}} zmm3 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: vpmuldq %zmm1, %zmm3, %zmm1
; AVX-NEXT: addl %eax, %ecx ; AVX-NEXT: vmovdqa32 {{.*#+}} zmm3 = [1,17,3,19,5,21,7,23,9,25,11,27,13,29,15,31]
; AVX-NEXT: movl %ecx, %edx ; AVX-NEXT: vpermi2d %zmm1, %zmm2, %zmm3
; AVX-NEXT: shrl $31, %edx ; AVX-NEXT: vpaddd %zmm0, %zmm3, %zmm1
; AVX-NEXT: sarl $2, %ecx ; AVX-NEXT: vpsrld $31, %zmm1, %zmm2
; AVX-NEXT: addl %edx, %ecx ; AVX-NEXT: vpsrad $2, %zmm1, %zmm1
; AVX-NEXT: leal (,%rcx,8), %edx ; AVX-NEXT: vpaddd %zmm2, %zmm1, %zmm1
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm1, %zmm1
; AVX-NEXT: subl %edx, %eax ; AVX-NEXT: vpsubd %zmm1, %zmm0, %zmm0
; AVX-NEXT: vmovd %xmm1, %ecx
; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: movl %edx, %esi
; AVX-NEXT: shrl $31, %esi
; AVX-NEXT: sarl $2, %edx
; AVX-NEXT: addl %esi, %edx
; AVX-NEXT: leal (,%rdx,8), %esi
; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: subl %esi, %ecx
; AVX-NEXT: vmovd %ecx, %xmm2
; AVX-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $2, %xmm1, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $3, %xmm1, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm2, %xmm1
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: movl %edx, %esi
; AVX-NEXT: shrl $31, %esi
; AVX-NEXT: sarl $2, %edx
; AVX-NEXT: addl %esi, %edx
; AVX-NEXT: leal (,%rdx,8), %esi
; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: subl %esi, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: movl %edx, %esi
; AVX-NEXT: shrl $31, %esi
; AVX-NEXT: sarl $2, %edx
; AVX-NEXT: addl %esi, %edx
; AVX-NEXT: leal (,%rdx,8), %esi
; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: subl %esi, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vpextrd $1, %xmm0, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vmovd %xmm0, %ecx
; AVX-NEXT: movslq %ecx, %rcx
; AVX-NEXT: imulq $-1840700269, %rcx, %rdx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: movl %edx, %esi
; AVX-NEXT: shrl $31, %esi
; AVX-NEXT: sarl $2, %edx
; AVX-NEXT: addl %esi, %edx
; AVX-NEXT: leal (,%rdx,8), %esi
; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: subl %esi, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm0, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm0, %eax
; AVX-NEXT: cltq
; AVX-NEXT: imulq $-1840700269, %rax, %rcx # imm = 0x92492493
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: addl %eax, %ecx
; AVX-NEXT: movl %ecx, %edx
; AVX-NEXT: shrl $31, %edx
; AVX-NEXT: sarl $2, %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: leal (,%rcx,8), %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: subl %edx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm0
; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%res = srem <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> %res = srem <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
ret <16 x i32> %res ret <16 x i32> %res
} }
define <32 x i16> @test_rem7_32i16(<32 x i16> %a) nounwind { define <32 x i16> @test_rem7_32i16(<32 x i16> %a) nounwind {
; AVX512F-LABEL: test_rem7_32i16: ; AVX512F-LABEL: test_rem7_32i16:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
▲ Show 20 Lines • Show All 1,009 Lines • Show Last 20 Lines

test/CodeGen/X86/vector-idiv-udiv-512.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; AVX-NEXT: retq ; AVX-NEXT: retq
%res = udiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7> %res = udiv <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res ret <8 x i64> %res
} }
define <16 x i32> @test_div7_16i32(<16 x i32> %a) nounwind { define <16 x i32> @test_div7_16i32(<16 x i32> %a) nounwind {
; AVX-LABEL: test_div7_16i32: ; AVX-LABEL: test_div7_16i32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; AVX-NEXT: vpbroadcastd {{.*#+}} zmm1 = [613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757]
; AVX-NEXT: vpextrd $1, %xmm1, %eax ; AVX-NEXT: vpmuludq %zmm1, %zmm0, %zmm2
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925 ; AVX-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: vpshufd {{.*#+}} zmm3 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: subl %ecx, %eax ; AVX-NEXT: vpmuludq %zmm1, %zmm3, %zmm1
; AVX-NEXT: shrl %eax ; AVX-NEXT: vmovdqa32 {{.*#+}} zmm3 = [1,17,3,19,5,21,7,23,9,25,11,27,13,29,15,31]
; AVX-NEXT: addl %ecx, %eax ; AVX-NEXT: vpermi2d %zmm1, %zmm2, %zmm3
; AVX-NEXT: shrl $2, %eax ; AVX-NEXT: vpsubd %zmm3, %zmm0, %zmm0
; AVX-NEXT: vmovd %xmm1, %ecx ; AVX-NEXT: vpsrld $1, %zmm0, %zmm0
; AVX-NEXT: imulq $613566757, %rcx, %rdx # imm = 0x24924925 ; AVX-NEXT: vpaddd %zmm3, %zmm0, %zmm0
; AVX-NEXT: shrq $32, %rdx ; AVX-NEXT: vpsrld $2, %zmm0, %zmm0
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: shrl %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: shrl $2, %ecx
; AVX-NEXT: vmovd %ecx, %xmm2
; AVX-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $2, %xmm1, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $3, %xmm1, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm2, %xmm1
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: imulq $613566757, %rcx, %rdx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: shrl %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: shrl $2, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: imulq $613566757, %rcx, %rdx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: shrl %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: shrl $2, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vpextrd $1, %xmm0, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vmovd %xmm0, %ecx
; AVX-NEXT: imulq $613566757, %rcx, %rdx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: shrl %ecx
; AVX-NEXT: addl %edx, %ecx
; AVX-NEXT: shrl $2, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm0, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm0, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: shrl %eax
; AVX-NEXT: addl %ecx, %eax
; AVX-NEXT: shrl $2, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm0
; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%res = udiv <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> %res = udiv <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
ret <16 x i32> %res ret <16 x i32> %res
} }
define <32 x i16> @test_div7_32i16(<32 x i16> %a) nounwind { define <32 x i16> @test_div7_32i16(<32 x i16> %a) nounwind {
; AVX512F-LABEL: test_div7_32i16: ; AVX512F-LABEL: test_div7_32i16:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
▲ Show 20 Lines • Show All 771 Lines • ▼ Show 20 Lines
; AVX-NEXT: retq ; AVX-NEXT: retq
%res = urem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7> %res = urem <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
ret <8 x i64> %res ret <8 x i64> %res
} }
define <16 x i32> @test_rem7_16i32(<16 x i32> %a) nounwind { define <16 x i32> @test_rem7_16i32(<16 x i32> %a) nounwind {
; AVX-LABEL: test_rem7_16i32: ; AVX-LABEL: test_rem7_16i32:
; AVX: # BB#0: ; AVX: # BB#0:
; AVX-NEXT: vextracti32x4 $3, %zmm0, %xmm1 ; AVX-NEXT: vpbroadcastd {{.*#+}} zmm1 = [613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757,613566757]
; AVX-NEXT: vpextrd $1, %xmm1, %eax ; AVX-NEXT: vpmuludq %zmm1, %zmm0, %zmm2
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925 ; AVX-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: shrq $32, %rcx ; AVX-NEXT: vpshufd {{.*#+}} zmm3 = zmm0[1,1,3,3,5,5,7,7,9,9,11,11,13,13,15,15]
; AVX-NEXT: movl %eax, %edx ; AVX-NEXT: vpmuludq %zmm1, %zmm3, %zmm1
; AVX-NEXT: subl %ecx, %edx ; AVX-NEXT: vmovdqa32 {{.*#+}} zmm3 = [1,17,3,19,5,21,7,23,9,25,11,27,13,29,15,31]
; AVX-NEXT: shrl %edx ; AVX-NEXT: vpermi2d %zmm1, %zmm2, %zmm3
; AVX-NEXT: addl %ecx, %edx ; AVX-NEXT: vpsubd %zmm3, %zmm0, %zmm1
; AVX-NEXT: shrl $2, %edx ; AVX-NEXT: vpsrld $1, %zmm1, %zmm1
; AVX-NEXT: leal (,%rdx,8), %ecx ; AVX-NEXT: vpaddd %zmm3, %zmm1, %zmm1
; AVX-NEXT: subl %edx, %ecx ; AVX-NEXT: vpsrld $2, %zmm1, %zmm1
; AVX-NEXT: subl %ecx, %eax ; AVX-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm1, %zmm1
; AVX-NEXT: vmovd %xmm1, %ecx ; AVX-NEXT: vpsubd %zmm1, %zmm0, %zmm0
; AVX-NEXT: imulq $613566757, %rcx, %rdx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: movl %ecx, %esi
; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: shrl %esi
; AVX-NEXT: addl %edx, %esi
; AVX-NEXT: shrl $2, %esi
; AVX-NEXT: leal (,%rsi,8), %edx
; AVX-NEXT: subl %esi, %edx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm2
; AVX-NEXT: vpinsrd $1, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $2, %xmm1, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm2, %xmm2
; AVX-NEXT: vpextrd $3, %xmm1, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm2, %xmm1
; AVX-NEXT: vextracti32x4 $2, %zmm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: imulq $613566757, %rcx, %rdx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: movl %ecx, %esi
; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: shrl %esi
; AVX-NEXT: addl %edx, %esi
; AVX-NEXT: shrl $2, %esi
; AVX-NEXT: leal (,%rsi,8), %edx
; AVX-NEXT: subl %esi, %edx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
; AVX-NEXT: vextracti128 $1, %ymm0, %xmm2
; AVX-NEXT: vpextrd $1, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vmovd %xmm2, %ecx
; AVX-NEXT: imulq $613566757, %rcx, %rdx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: movl %ecx, %esi
; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: shrl %esi
; AVX-NEXT: addl %edx, %esi
; AVX-NEXT: shrl $2, %esi
; AVX-NEXT: leal (,%rsi,8), %edx
; AVX-NEXT: subl %esi, %edx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm2, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm2
; AVX-NEXT: vpextrd $1, %xmm0, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vmovd %xmm0, %ecx
; AVX-NEXT: imulq $613566757, %rcx, %rdx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rdx
; AVX-NEXT: movl %ecx, %esi
; AVX-NEXT: subl %edx, %esi
; AVX-NEXT: shrl %esi
; AVX-NEXT: addl %edx, %esi
; AVX-NEXT: shrl $2, %esi
; AVX-NEXT: leal (,%rsi,8), %edx
; AVX-NEXT: subl %esi, %edx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: vmovd %ecx, %xmm3
; AVX-NEXT: vpinsrd $1, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $2, %xmm0, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vpinsrd $2, %eax, %xmm3, %xmm3
; AVX-NEXT: vpextrd $3, %xmm0, %eax
; AVX-NEXT: imulq $613566757, %rax, %rcx # imm = 0x24924925
; AVX-NEXT: shrq $32, %rcx
; AVX-NEXT: movl %eax, %edx
; AVX-NEXT: subl %ecx, %edx
; AVX-NEXT: shrl %edx
; AVX-NEXT: addl %ecx, %edx
; AVX-NEXT: shrl $2, %edx
; AVX-NEXT: leal (,%rdx,8), %ecx
; AVX-NEXT: subl %edx, %ecx
; AVX-NEXT: subl %ecx, %eax
; AVX-NEXT: vpinsrd $3, %eax, %xmm3, %xmm0
; AVX-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
; AVX-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
; AVX-NEXT: retq ; AVX-NEXT: retq
%res = urem <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> %res = urem <16 x i32> %a, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
ret <16 x i32> %res ret <16 x i32> %res
} }
define <32 x i16> @test_rem7_32i16(<32 x i16> %a) nounwind { define <32 x i16> @test_rem7_32i16(<32 x i16> %a) nounwind {
; AVX512F-LABEL: test_rem7_32i16: ; AVX512F-LABEL: test_rem7_32i16:
; AVX512F: # BB#0: ; AVX512F: # BB#0:
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