ARMEB: Additional test files for ARM fixups

[cpirker]

Summary

Hi all,

I add two asserts in the ARM fixup handling routine to check valid values for "FullSizeBytes."
This patch also adds test files for fixups in big endian ARM mode.
Please review.

Thanks,
Christian

[rengolin]

Hi Christian,

Is it possible to add a test to catch the asserts when enabled?

Otherwise, LGTM.

thanks,
--renato

[Konrad]

Hi Renato,

You would need to change llvm source code to enable the asserts, as they check invalid constants.

cheers,
Conny

[rengolin]

Right, thought so.

cheers,
--renato

[cpirker]

I committed this patch as rL209200.

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
   Value = adjustFixupValue(Fixup, Value, IsPCRel, nullptr, IsLittleEndian);
   if (!Value) return;           // Doesn't change encoding.
 
   unsigned Offset = Fixup.getOffset();
   assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
 
   // Used to point to big endian bytes.
   unsigned FullSizeBytes;
-  if (!IsLittleEndian)
+  if (!IsLittleEndian) {
     FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
+    assert((Offset + FullSizeBytes) <= DataSize && "Invalid fixup size!");
+    assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
+  }
 
   // For each byte of the fragment that the fixup touches, mask in the bits from
   // the fixup value. The Value has been "split up" into the appropriate
   // bitfields above.
   for (unsigned i = 0; i != NumBytes; ++i) {
     unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i);
     Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
   }

test/MC/ARM/big-endian-arm-fixup.s

+// RUN: llvm-mc -triple=armeb-eabi -mattr v7,vfp2 -filetype=obj < %s | llvm-objdump -s - | FileCheck %s
+
+  .syntax unified
+  .text
+  .align  2
+  .code 32
+
+@ARM::fixup_arm_condbl
+.section s_condbl,"ax",%progbits
+// CHECK-LABEL: Contents of section s_condbl
+// CHECK: 0000 0b000002
+  bleq condbl_label+16
+condbl_label:
+
+@ARM::fixup_arm_uncondbl
+.section s_uncondbl,"ax",%progbits
+// CHECK-LABEL: Contents of section s_uncondbl
+// CHECK: 0000 eb000002
+  bl uncond_label+16
+uncond_label:
+
+@ARM::fixup_arm_blx
+.section s_blx,"ax",%progbits
+// CHECK-LABEL: Contents of section s_blx
+// CHECK: 0000 fa000002
+  blx blx_label+16
+blx_label:
+
+@ARM::fixup_arm_uncondbranch
+.section s_uncondbranch,"ax",%progbits
+// CHECK-LABEL: Contents of section s_uncondbranch
+// CHECK: 0000 ea000003
+  b uncondbranch_label+16
+uncondbranch_label:
+
+@ARM::fixup_arm_condbranch
+.section s_condbranch,"ax",%progbits
+// CHECK-LABEL: Contents of section s_condbranch
+// CHECK: 0000 0a000003
+  beq condbranch_label+16
+condbranch_label:
+
+@ARM::fixup_arm_pcrel_10
+.section s_arm_pcrel_10,"ax",%progbits
+// CHECK-LABEL: Contents of section s_arm_pcrel_10
+// CHECK: 0000 ed9f0b03
+  vldr d0, arm_pcrel_10_label+16
+arm_pcrel_10_label:
+
+@ARM::fixup_arm_ldst_pcrel_12
+.section s_arm_ldst_pcrel_12,"ax",%progbits
+// CHECK-LABEL: Contents of section s_arm_ldst_pcrel_12
+// CHECK: 0000 e59f000c
+  ldr r0, arm_ldst_pcrel_12_label+16
+arm_ldst_pcrel_12_label:
+
+@ARM::fixup_arm_adr_pcrel_12
+.section s_arm_adr_pcrel_12,"ax",%progbits
+// CHECK-LABEL: Contents of section s_arm_adr_pcrel_12
+// CHECK: 0000 e28f0010
+  adr r0, arm_adr_pcrel_12_label+20
+arm_adr_pcrel_12_label:
+
+@ARM::fixup_arm_adr_pcrel_10_unscaled
+.section s_arm_adr_pcrel_10_unscaled,"ax",%progbits
+// CHECK-LABEL: Contents of section s_arm_adr_pcrel_10_unscaled
+// CHECK: 0000 e1cf01d4
+  ldrd  r0, r1, arm_adr_pcrel_10_unscaled_label+24
+arm_adr_pcrel_10_unscaled_label:
+
+@ARM::fixup_arm_movw_lo16
+.section s_movw,"ax",%progbits
+// CHECK-LABEL: Contents of section s_movw
+// CHECK: 0000 e3000008
+  movw  r0, :lower16:(some_label+8)
+
+@ARM::fixup_arm_movt_hi16
+.section s_movt,"ax",%progbits
+// CHECK-LABEL: Contents of section s_movt
+// CHECK: 0000 e34f0ffc
+  movt  r0, :upper16:GOT-(movt_label)
+movt_label:
+
+@FK_Data_1
+.section s_fk_data_1
+// CHECK-LABEL: Contents of section s_fk_data_1
+// CHECK: 0000 01
+fk_data1_l_label:
+.byte fk_data1_h_label-fk_data1_l_label
+fk_data1_h_label:
+
+@FK_Data_2
+.section s_fk_data_2
+// CHECK-LABEL: Contents of section s_fk_data_2
+// CHECK: 0000 0002
+fk_data2_l_label:
+.short fk_data2_h_label-fk_data2_l_label
+fk_data2_h_label:
+
+@FK_Data_4
+.section s_fk_data_4
+// CHECK-LABEL: Contents of section s_fk_data_4
+// CHECK: 0000 00000004
+fk_data4_l_label:
+.long fk_data4_h_label-fk_data4_l_label
+fk_data4_h_label:
+

test/MC/ARM/big-endian-thumb-fixup.s

+// RUN: llvm-mc -triple=armeb-eabi -mattr v7,vfp2 -filetype=obj < %s | llvm-objdump -s - | FileCheck %s
+
+  .syntax unified
+  .text
+  .align  2
+  .code 16
+
+@ARM::fixup_arm_thumb_bl
+.section s_thumb_bl,"ax",%progbits
+// CHECK-LABEL: Contents of section s_thumb_bl
+// CHECK: 0000 f000f801
+  bl thumb_bl_label
+  nop
+thumb_bl_label:
+
+@ARM::fixup_arm_thumb_blx
+// CHECK-LABEL: Contents of section s_thumb_bl
+// CHECK: 0000 f000e802
+.section s_thumb_blx,"ax",%progbits
+  blx thumb_blx_label+8
+thumb_blx_label:
+
+@ARM::fixup_arm_thumb_br
+.section s_thumb_br,"ax",%progbits
+// CHECK-LABEL: Contents of section s_thumb_br
+// CHECK: 0000 e000bf00
+  b thumb_br_label
+  nop
+thumb_br_label:
+
+@ARM::fixup_arm_thumb_bcc
+.section s_thumb_bcc,"ax",%progbits
+// CHECK-LABEL: Contents of section s_thumb_bcc
+// CHECK: 0000 d000bf00
+  beq thumb_bcc_label
+  nop
+thumb_bcc_label:
+
+@ARM::fixup_arm_thumb_cb
+.section s_thumb_cb,"ax",%progbits
+// CHECK-LABEL: Contents of section s_thumb_cb
+// CHECK: 0000 b100bf00
+  cbz r0, thumb_cb_label
+  nop
+thumb_cb_label:
+
+@ARM::fixup_arm_thumb_cp
+.section s_thumb_cp,"ax",%progbits
+// CHECK-LABEL: Contents of section s_thumb_cp
+// CHECK: 0000 4801bf00
+  ldr r0, =thumb_cp_label
+  nop
+  nop
+thumb_cp_label:
+
+@ARM::fixup_arm_thumb_adr_pcrel_10
+.section s_thumb_adr_pcrel_10,"ax",%progbits
+// CHECK-LABEL: Contents of section s_thumb_adr_pcrel_10
+// CHECK: 0000 a000bf00
+  adr r0, thumb_adr_pcrel_10_label
+  nop
+thumb_adr_pcrel_10_label:
+

test/MC/ARM/big-endian-thumb2-fixup.s

+// RUN: llvm-mc -triple=thumbeb-eabi -mattr v7,vfp2 -filetype=obj < %s | llvm-objdump -s - | FileCheck %s
+
+  .syntax unified
+  .text
+  .align  2
+
+@ARM::fixup_t2_movw_lo16
+.section s_movw,"ax",%progbits
+// CHECK-LABEL: Contents of section s_movw
+// CHECK: 0000 f2400008
+  movw  r0, :lower16:(some_label+8)
+
+@ARM::fixup_t2_movt_hi16
+.section s_movt,"ax",%progbits
+// CHECK-LABEL: Contents of section s_movt
+// CHECK: 0000 f6cf70fc
+  movt  r0, :upper16:GOT-(movt_label)
+movt_label:
+
+@ARM::fixup_t2_uncondbranch
+.section s_uncondbranch,"ax",%progbits
+// CHECK-LABEL: Contents of section s_uncondbranch
+// CHECK: 0000 f000b801 bf00
+  b.w uncond_label
+  nop
+uncond_label:
+
+@ARM::fixup_t2_condbranch
+.section s_condbranch,"ax",%progbits
+// CHECK-LABEL: Contents of section s_condbranch
+// CHECK: 0000 f0008001 bf00
+  beq.w cond_label
+  nop
+cond_label:
+
+@ARM::fixup_t2_ldst_precel_12
+.section s_ldst_precel_12,"ax",%progbits
+  ldr r0, ldst_precel_12_label
+  nop
+  nop
+ldst_precel_12_label:
+
+@ARM::fixup_t2_adr_pcrel_12
+.section s_adr_pcrel_12,"ax",%progbits
+  adr r0, adr_pcrel_12_label
+  nop
+  nop
+adr_pcrel_12_label:
+