Hexagon: Add encoding bits for vector multiply instructions.

[jverma]

Summary

This patch adds encoding bits for vector multiply instructions for the Hexagon backend.

[Eugene.Zelenko]

Looks like patch was not committed.

lib/Target/Hexagon/HexagonIntrinsics.td

 def HEXAGON_M2_mpy_nac_sat_hh_s0 :
              T_M2_mpy_acc < 0b11, 1, 1, 0, 0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 
+
+//===----------------------------------------------------------------------===//
+// Template Class -- Vector Multipy
+// Used for complex multiply real or imaginary, dual multiply and even halfwords
+//===----------------------------------------------------------------------===//
+class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift,
+                  bit isRnd, bit isSat, Intrinsic IntID >
+  : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
+  "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","")
+                              #!if(isRnd,":rnd","")
+                              #!if(isSat,":sat",""),
+  [(set DoubleRegs:$Rdd, (IntID DoubleRegs:$Rss, DoubleRegs:$Rtt))] > {
+    bits<5> Rdd;
+    bits<5> Rss;
+    bits<5> Rtt;
+
+    let IClass = 0b1110;
+
+    let Inst{27-24} = 0b1000;
+    let Inst{23-21} = MajOp;
+    let Inst{7-5} = MinOp;
+    let Inst{4-0} = Rdd;
+    let Inst{20-16} = Rss;
+    let Inst{12-8} = Rtt;
+  }
+
+// Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
+let Defs = [USR] in {
+def HEXAGON_M2_vcmpy_s1_sat_i :
+    T_M2_vmpy < "vcmpyi", 0b110, 0b110, 1, 0, 1, int_hexagon_M2_vcmpy_s1_sat_i>;
+def HEXAGON_M2_vcmpy_s0_sat_i :
+    T_M2_vmpy < "vcmpyi", 0b010, 0b110, 0, 0, 1, int_hexagon_M2_vcmpy_s0_sat_i>;
+
+// Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
+def HEXAGON_M2_vcmpy_s1_sat_r :
+    T_M2_vmpy < "vcmpyr", 0b101, 0b110, 1, 0, 1, int_hexagon_M2_vcmpy_s1_sat_r>;
+def HEXAGON_M2_vcmpy_s0_sat_r :
+    T_M2_vmpy < "vcmpyr", 0b001, 0b110, 0, 0, 1, int_hexagon_M2_vcmpy_s0_sat_r>;
+
+// Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
+def HEXAGON_M2_vdmpys_s1 :
+          T_M2_vmpy < "vdmpy", 0b100, 0b100, 1, 0, 1, int_hexagon_M2_vdmpys_s1>;
+def HEXAGON_M2_vdmpys_s0 :
+          T_M2_vmpy < "vdmpy", 0b000, 0b100, 0, 0, 1, int_hexagon_M2_vdmpys_s0>;
+
+// Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
+def HEXAGON_M2_vmpy2es_s1 :
+        T_M2_vmpy < "vmpyeh", 0b100, 0b110, 1, 0, 1, int_hexagon_M2_vmpy2es_s1>;
+def HEXAGON_M2_vmpy2es_s0 :
+        T_M2_vmpy < "vmpyeh", 0b000, 0b110, 0, 0, 1, int_hexagon_M2_vmpy2es_s0>;
+
+
+//Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
+def HEXAGON_M2_mmpyh_s0 :
+         T_M2_vmpy < "vmpywoh", 0b000, 0b111, 0, 0, 1, int_hexagon_M2_mmpyh_s0>;
+def HEXAGON_M2_mmpyh_s1 :
+         T_M2_vmpy < "vmpywoh", 0b100, 0b111, 1, 0, 1, int_hexagon_M2_mmpyh_s1>;
+def HEXAGON_M2_mmpyh_rs0 :
+        T_M2_vmpy < "vmpywoh", 0b001, 0b111, 0, 1, 1, int_hexagon_M2_mmpyh_rs0>;
+def HEXAGON_M2_mmpyh_rs1 :
+        T_M2_vmpy < "vmpywoh", 0b101, 0b111, 1, 1, 1, int_hexagon_M2_mmpyh_rs1>;
+
+//Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
+def HEXAGON_M2_mmpyl_s0 :
+         T_M2_vmpy < "vmpyweh", 0b000, 0b101, 0, 0, 1, int_hexagon_M2_mmpyl_s0>;
+def HEXAGON_M2_mmpyl_s1 :
+         T_M2_vmpy < "vmpyweh", 0b100, 0b101, 1, 0, 1, int_hexagon_M2_mmpyl_s1>;
+def HEXAGON_M2_mmpyl_rs0 :
+        T_M2_vmpy < "vmpyweh", 0b001, 0b101, 0, 1, 1, int_hexagon_M2_mmpyl_rs0>;
+def HEXAGON_M2_mmpyl_rs1 :
+        T_M2_vmpy < "vmpyweh", 0b101, 0b101, 1, 1, 1, int_hexagon_M2_mmpyl_rs1>;
+
+//Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
+def HEXAGON_M2_mmpyuh_s0 :
+       T_M2_vmpy < "vmpywouh", 0b010, 0b111, 0, 0, 1, int_hexagon_M2_mmpyuh_s0>;
+def HEXAGON_M2_mmpyuh_s1 :
+       T_M2_vmpy < "vmpywouh", 0b110, 0b111, 1, 0, 1, int_hexagon_M2_mmpyuh_s1>;
+def HEXAGON_M2_mmpyuh_rs0 :
+      T_M2_vmpy < "vmpywouh", 0b011, 0b111, 0, 1, 1, int_hexagon_M2_mmpyuh_rs0>;
+def HEXAGON_M2_mmpyuh_rs1 :
+      T_M2_vmpy < "vmpywouh", 0b111, 0b111, 1, 1, 1, int_hexagon_M2_mmpyuh_rs1>;
+
+//Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
+def HEXAGON_M2_mmpyul_s0 :
+       T_M2_vmpy < "vmpyweuh", 0b010, 0b101, 0, 0, 1, int_hexagon_M2_mmpyul_s0>;
+def HEXAGON_M2_mmpyul_s1 :
+       T_M2_vmpy < "vmpyweuh", 0b110, 0b101, 1, 0, 1, int_hexagon_M2_mmpyul_s1>;
+def HEXAGON_M2_mmpyul_rs0 :
+      T_M2_vmpy < "vmpyweuh", 0b011, 0b101, 0, 1, 1, int_hexagon_M2_mmpyul_rs0>;
+def HEXAGON_M2_mmpyul_rs1 :
+      T_M2_vmpy < "vmpyweuh", 0b111, 0b101, 1, 1, 1, int_hexagon_M2_mmpyul_rs1>;
+}
+
+//===----------------------------------------------------------------------===//
+// Template Class -- XType Vector Instructions
+//===----------------------------------------------------------------------===//
+class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj,
+                     Intrinsic IntID >
+  : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
+  "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
+  [(set DoubleRegs:$Rdd, (IntID DoubleRegs:$Rss, DoubleRegs:$Rtt))] > {
+    bits<5> Rdd;
+    bits<5> Rss;
+    bits<5> Rtt;
+
+    let IClass = 0b1110;
+
+    let Inst{27-24} = 0b1000;
+    let Inst{23-21} = MajOp;
+    let Inst{7-5} = MinOp;
+    let Inst{4-0} = Rdd;
+    let Inst{20-16} = Rss;
+    let Inst{12-8} = Rtt;
+  }
+
+class T_XTYPE_Vect_diff < bits<3> MajOp, string opc, Intrinsic IntID >
+  : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss),
+  "$Rdd = "#opc#"($Rtt, $Rss)",
+  [(set DoubleRegs:$Rdd, (IntID DoubleRegs:$Rtt, DoubleRegs:$Rss))],
+    "",M_tc_2_SLOT23 > {
+    bits<5> Rdd;
+    bits<5> Rss;
+    bits<5> Rtt;
+
+    let IClass = 0b1110;
+
+    let Inst{27-24} = 0b1000;
+    let Inst{23-21} = MajOp;
+    let Inst{7-5} = 0b000;
+    let Inst{4-0} = Rdd;
+    let Inst{20-16} = Rss;
+    let Inst{12-8} = Rtt;
+  }
+
+// Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32)
+def HEXAGON_A2_vraddub : T_XTYPE_Vect
+                  < "vraddub", 0b010, 0b001, 0, int_hexagon_A2_vraddub>;
+
+// Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
+def HEXAGON_A2_vrsadub : T_XTYPE_Vect
+                  < "vrsadub", 0b010, 0b010, 0, int_hexagon_A2_vrsadub>;
+
+// Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
+def HEXAGON_M2_vabsdiffh :
+         T_XTYPE_Vect_diff < 0b011, "vabsdiffh", int_hexagon_M2_vabsdiffh>;
+
+// Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
+def HEXAGON_M2_vabsdiffw :
+         T_XTYPE_Vect_diff < 0b001, "vabsdiffw", int_hexagon_M2_vabsdiffw>;
+
+// Vector reduce complex multiply real or imaginary:
+// Rdd=vrcmpy[ir](Rss,Rtt[*])
+def HEXAGON_M2_vrcmpyi_s0 : T_XTYPE_Vect
+                  < "vrcmpyi", 0b000, 0b000, 0, int_hexagon_M2_vrcmpyi_s0>;
+def HEXAGON_M2_vrcmpyi_s0c : T_XTYPE_Vect
+                  < "vrcmpyi", 0b010, 0b000, 1, int_hexagon_M2_vrcmpyi_s0c>;
+def HEXAGON_M2_vrcmpyr_s0 : T_XTYPE_Vect
+                  < "vrcmpyr", 0b000, 0b001, 0, int_hexagon_M2_vrcmpyr_s0>;
+def HEXAGON_M2_vrcmpyr_s0c : T_XTYPE_Vect
+                  < "vrcmpyr", 0b011, 0b001, 1, int_hexagon_M2_vrcmpyr_s0c>;
+
+// Vector reduce multiply halfwords: Rdd=vrmpyh(Rss,Rtt)
+def HEXAGON_M2_vrmpy_s0 : T_XTYPE_Vect
+                  < "vrmpyh", 0b000, 0b010, 0, int_hexagon_M2_vrmpy_s0>;
+
 //
 // ALU 32 types.
 //

              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
                                            DoubleRegs:$src2))]>;
 
-class di_MInst_didi_conj<string opc, Intrinsic IntID>
-  : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
-             !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
-             [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
-                                           DoubleRegs:$src2))]>;
-
 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
              !strconcat("$dst = ", !strconcat(opc ,
                                               "($src1, $src2*):<<1:sat")),
              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 
-class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
-  : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
-             !strconcat("$dst = ", !strconcat(opc ,
-                                              "($src1, $src2):<<1:rnd:sat")),
-             [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
-                                           DoubleRegs:$src2))]>;
-
 class di_MInst_didi_sat<string opc, Intrinsic IntID>
   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
                                            DoubleRegs:$src2))]>;
 
-class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
-  : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
-             !strconcat("$dst = ", !strconcat(opc ,
-                                              "($src1, $src2):rnd:sat")),
-             [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
-                                           DoubleRegs:$src2))]>;
-
 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),

              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 
-class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
-  : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
-             !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
-             [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
-                                           DoubleRegs:$src2))]>;
-
 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
              !strconcat("$dst = ", !strconcat(opc ,

 def HEXAGON_M2_subacc:
   si_MInst_sisisi_acc             <"sub",      int_hexagon_M2_subacc>;
 
-// MTYPE / ALU / Vector absolute difference.
-def HEXAGON_M2_vabsdiffh:
-  di_MInst_didi                   <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
-def HEXAGON_M2_vabsdiffw:
-  di_MInst_didi                   <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
-
 // MTYPE / ALU / XOR and xor with destination.
 def HEXAGON_M2_xor_xacc:
   si_MInst_sisisi_xacc            <"xor",      int_hexagon_M2_xor_xacc>;

   si_MInst_sisi_s1_rnd_sat_conj   <"cmpy",     int_hexagon_M2_cmpyrsc_s1>;
 
 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
-def HEXAGON_M2_vcmpy_s0_sat_i:
-  di_MInst_didi_sat               <"vcmpyi",   int_hexagon_M2_vcmpy_s0_sat_i>;
-def HEXAGON_M2_vcmpy_s1_sat_i:
-  di_MInst_didi_s1_sat            <"vcmpyi",   int_hexagon_M2_vcmpy_s1_sat_i>;
-
-def HEXAGON_M2_vcmpy_s0_sat_r:
-  di_MInst_didi_sat               <"vcmpyr",   int_hexagon_M2_vcmpy_s0_sat_r>;
-def HEXAGON_M2_vcmpy_s1_sat_r:
-  di_MInst_didi_s1_sat            <"vcmpyr",   int_hexagon_M2_vcmpy_s1_sat_r>;
 
 def HEXAGON_M2_vcmac_s0_sat_i:
   di_MInst_dididi_acc_sat         <"vcmpyi",   int_hexagon_M2_vcmac_s0_sat_i>;
 def HEXAGON_M2_vcmac_s0_sat_r:
   di_MInst_dididi_acc_sat         <"vcmpyr",   int_hexagon_M2_vcmac_s0_sat_r>;
 
-//MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
-def HEXAGON_M2_vrcmpyi_s0:
-  di_MInst_didi                   <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0>;
-def HEXAGON_M2_vrcmpyr_s0:
-  di_MInst_didi                   <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0>;
-
-def HEXAGON_M2_vrcmpyi_s0c:
-  di_MInst_didi_conj              <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0c>;
-def HEXAGON_M2_vrcmpyr_s0c:
-  di_MInst_didi_conj              <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0c>;
-
 def HEXAGON_M2_vrcmaci_s0:
   di_MInst_dididi_acc             <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0>;
 def HEXAGON_M2_vrcmacr_s0:

 // MTYPE / MPYH / Multiply word by half (32x16).
 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
-def HEXAGON_M2_mmpyl_rs1:
-  di_MInst_didi_s1_rnd_sat        <"vmpyweh",  int_hexagon_M2_mmpyl_rs1>;
-def HEXAGON_M2_mmpyl_s1:
-  di_MInst_didi_s1_sat            <"vmpyweh",  int_hexagon_M2_mmpyl_s1>;
-def HEXAGON_M2_mmpyl_rs0:
-  di_MInst_didi_rnd_sat           <"vmpyweh",  int_hexagon_M2_mmpyl_rs0>;
-def HEXAGON_M2_mmpyl_s0:
-  di_MInst_didi_sat               <"vmpyweh",  int_hexagon_M2_mmpyl_s0>;
-def HEXAGON_M2_mmpyh_rs1:
-  di_MInst_didi_s1_rnd_sat        <"vmpywoh",  int_hexagon_M2_mmpyh_rs1>;
-def HEXAGON_M2_mmpyh_s1:
-  di_MInst_didi_s1_sat            <"vmpywoh",  int_hexagon_M2_mmpyh_s1>;
-def HEXAGON_M2_mmpyh_rs0:
-  di_MInst_didi_rnd_sat           <"vmpywoh",  int_hexagon_M2_mmpyh_rs0>;
-def HEXAGON_M2_mmpyh_s0:
-  di_MInst_didi_sat               <"vmpywoh",  int_hexagon_M2_mmpyh_s0>;
 def HEXAGON_M2_mmacls_rs1:
   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweh",  int_hexagon_M2_mmacls_rs1>;
 def HEXAGON_M2_mmacls_s1:

 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
-def HEXAGON_M2_mmpyul_rs1:
-  di_MInst_didi_s1_rnd_sat        <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
-def HEXAGON_M2_mmpyul_s1:
-  di_MInst_didi_s1_sat            <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
-def HEXAGON_M2_mmpyul_rs0:
-  di_MInst_didi_rnd_sat           <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
-def HEXAGON_M2_mmpyul_s0:
-  di_MInst_didi_sat               <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
-def HEXAGON_M2_mmpyuh_rs1:
-  di_MInst_didi_s1_rnd_sat        <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
-def HEXAGON_M2_mmpyuh_s1:
-  di_MInst_didi_s1_sat            <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
-def HEXAGON_M2_mmpyuh_rs0:
-  di_MInst_didi_rnd_sat           <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
-def HEXAGON_M2_mmpyuh_s0:
-  di_MInst_didi_sat               <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
 def HEXAGON_M2_mmaculs_rs1:
   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
 def HEXAGON_M2_mmaculs_s1:

 *            MTYPE/VB                                               *
 *********************************************************************/
 
-// MTYPE / VB / Vector reduce add unsigned bytes.
-def HEXAGON_A2_vraddub:
-  di_MInst_didi                   <"vraddub", int_hexagon_A2_vraddub>;
 def HEXAGON_A2_vraddub_acc:
   di_MInst_dididi_acc             <"vraddub", int_hexagon_A2_vraddub_acc>;
 
-// MTYPE / VB / Vector sum of absolute differences unsigned bytes.
-def HEXAGON_A2_vrsadub:
-  di_MInst_didi                   <"vrsadub", int_hexagon_A2_vrsadub>;
 def HEXAGON_A2_vrsadub_acc:
   di_MInst_dididi_acc             <"vrsadub", int_hexagon_A2_vrsadub_acc>;
 

 *********************************************************************/
 
 // MTYPE / VH / Vector dual multiply.
-def HEXAGON_M2_vdmpys_s1:
-  di_MInst_didi_s1_sat            <"vdmpy",   int_hexagon_M2_vdmpys_s1>;
-def HEXAGON_M2_vdmpys_s0:
-  di_MInst_didi_sat               <"vdmpy",   int_hexagon_M2_vdmpys_s0>;
 def HEXAGON_M2_vdmacs_s1:
   di_MInst_dididi_acc_s1_sat      <"vdmpy",   int_hexagon_M2_vdmacs_s1>;
 def HEXAGON_M2_vdmacs_s0:

   si_MInst_didi_s1_rnd_sat        <"vdmpy",   int_hexagon_M2_vdmpyrs_s1>;
 
 // MTYPE / VH / Vector multiply even halfwords.
-def HEXAGON_M2_vmpy2es_s1:
-  di_MInst_didi_s1_sat            <"vmpyeh",  int_hexagon_M2_vmpy2es_s1>;
-def HEXAGON_M2_vmpy2es_s0:
-  di_MInst_didi_sat               <"vmpyeh",  int_hexagon_M2_vmpy2es_s0>;
 def HEXAGON_M2_vmac2es:
   di_MInst_dididi_acc             <"vmpyeh",  int_hexagon_M2_vmac2es>;
 def HEXAGON_M2_vmac2es_s1:

   si_MInst_sisi_s1_rnd_sat        <"vmpyh",   int_hexagon_M2_vmpy2s_s1pack>;
 
 // MTYPE / VH / Vector reduce multiply halfwords.
-// Rxx32+=vrmpyh(Rss32,Rtt32)
-def HEXAGON_M2_vrmpy_s0:
-  di_MInst_didi                   <"vrmpyh",  int_hexagon_M2_vrmpy_s0>;
 def HEXAGON_M2_vrmac_s0:
   di_MInst_dididi_acc             <"vrmpyh",  int_hexagon_M2_vrmac_s0>;
 

lib/Target/Hexagon/HexagonIntrinsicsV4.td

 // 80-V9418-12 Rev. A
 // June 15, 2010
 
+// Vector reduce multiply word by signed half (32x16)
+//Rdd=vrmpyweh(Rss,Rtt)[:<<1]
+let Predicates = [HasV4T] in {
+def HEXAGON_M4_vrmpyeh_s0 :
+      T_M2_vmpy < "vrmpyweh", 0b010, 0b100, 0, 0, 0, int_hexagon_M4_vrmpyeh_s0>;
+def HEXAGON_M4_vrmpyeh_s1 :
+      T_M2_vmpy < "vrmpyweh", 0b110, 0b100, 1, 0, 0, int_hexagon_M4_vrmpyeh_s1>;
+
+//Rdd=vrmpywoh(Rss,Rtt)[:<<1]
+def HEXAGON_M4_vrmpyoh_s0 :
+      T_M2_vmpy < "vrmpywoh", 0b001, 0b010, 0, 0, 0, int_hexagon_M4_vrmpyoh_s0>;
+def HEXAGON_M4_vrmpyoh_s1 :
+      T_M2_vmpy < "vrmpywoh", 0b101, 0b010, 1, 0, 0, int_hexagon_M4_vrmpyoh_s1>;
+}
 
 //
 // ALU 32 types.

lib/Target/Hexagon/HexagonIntrinsicsV5.td

+//===- HexagonIntrinsicsV5.td - V5 Instruction intrinsics --*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//Rdd[+]=vrmpybsu(Rss,Rtt)
+let Predicates = [HasV5T], validSubTargets = HasV5SubT in
+def HEXAGON_M5_vrmpybsu : T_XTYPE_Vect
+                  < "vrmpybsu", 0b110, 0b001, 0, int_hexagon_M5_vrmpybsu>;
+def HEXAGON_M5_vrmacbsu : T_XTYPE_Vect_acc
+                  < "vrmpybsu", 0b110, 0b001, 0, int_hexagon_M5_vrmacbsu>;
+
+//Rdd[+]=vrmpybu(Rss,Rtt)
+let Predicates = [HasV5T], validSubTargets = HasV5SubT in
+def HEXAGON_M5_vrmpybuu : T_XTYPE_Vect
+                  < "vrmpybu", 0b100, 0b001, 0, int_hexagon_M5_vrmpybuu>;
+def HEXAGON_M5_vrmacbuu : T_XTYPE_Vect_acc
+                  < "vrmpybu", 0b100, 0b001, 0, int_hexagon_M5_vrmacbuu>;
+
 class sf_SInst_sf<string opc, Intrinsic IntID>
   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1),
              !strconcat("$dst = ", !strconcat(opc , "($src1)")),

     qi_SInst_qiqi       <"fastcorner9", int_hexagon_C4_fastcorner9>;
 def HEXAGON_C4_fastcorner9_not:
     qi_SInst_qiqi <"!fastcorner9", int_hexagon_C4_fastcorner9_not>;
-def HEXAGON_M5_vrmpybuu:
-    di_MInst_didi <"vrmpybu", int_hexagon_M5_vrmpybuu>;
 def HEXAGON_M5_vrmacbuu:
     di_MInst_dididi_acc <"vrmpybu", int_hexagon_M5_vrmacbuu>;
-def HEXAGON_M5_vrmpybsu:
-    di_MInst_didi <"vrmpybsu", int_hexagon_M5_vrmpybsu>;
 def HEXAGON_M5_vrmacbsu:
     di_MInst_dididi_acc <"vrmpybsu", int_hexagon_M5_vrmacbsu>;
 def HEXAGON_M5_vmpybuu:

test/CodeGen/Hexagon/intrinsics-vmpy.ll

+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+
+; Verify that the vector mpy intrinsics are lowered to the right instructions.
+
+@c = external global i64
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrcmpyi(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test1(i64 %a1, i64 %b1) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vrcmpyi.s0(i64 %a1, i64 %b1)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vrcmpyi.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrcmpyr(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test2(i64 %a2, i64 %b2) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vrcmpyr.s0(i64 %a2, i64 %b2)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vrcmpyr.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrmpyh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test3(i64 %a3, i64 %b3) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vrmpy.s0(i64 %a3, i64 %b3)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vrmpy.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vdmpy(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat
+
+define void @test4(i64 %a4, i64 %b4) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vdmpys.s0(i64 %a4, i64 %b4)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vdmpys.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat
+
+define void @test5(i64 %a5, i64 %b5) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyl.s0(i64 %a5, i64 %b5)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyl.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpyeh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat
+
+define void @test6(i64 %a6, i64 %b6) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vmpy2es.s0(i64 %a6, i64 %b6)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vmpy2es.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat
+
+define void @test7(i64 %a7, i64 %b7) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyh.s0(i64 %a7, i64 %b7)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyh.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vabsdiffw(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test8(i64 %a8, i64 %b8) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vabsdiffw(i64 %a8, i64 %b8)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vabsdiffw(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test9(i64 %a9, i64 %b9) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M4.vrmpyoh.s0(i64 %a9, i64 %b9)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M4.vrmpyoh.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):rnd:sat
+
+define void @test10(i64 %a10, i64 %b10) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyl.rs0(i64 %a10, i64 %b10)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyl.rs0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vcmpyr(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat
+
+define void @test11(i64 %a11, i64 %b11) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vcmpy.s0.sat.r(i64 %a11, i64 %b11)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vcmpy.s0.sat.r(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):rnd:sat
+
+define void @test12(i64 %a12, i64 %b12) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyh.rs0(i64 %a12, i64 %b12)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyh.rs0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrcmpyi(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}*)
+
+define void @test13(i64 %a13, i64 %b13) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vrcmpyi.s0c(i64 %a13, i64 %b13)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vrcmpyi.s0c(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vraddub(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test14(i64 %a14, i64 %b14) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A2.vraddub(i64 %a14, i64 %b14)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.A2.vraddub(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrsadub(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test15(i64 %a15, i64 %b15) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.A2.vrsadub(i64 %a15, i64 %b15)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.A2.vrsadub(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test16(i64 %a16, i64 %b16) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M4.vrmpyeh.s0(i64 %a16, i64 %b16)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M4.vrmpyeh.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpyweuh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat
+
+define void @test17(i64 %a17, i64 %b17) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyul.s0(i64 %a17, i64 %b17)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyul.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vcmpyi(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat
+
+define void @test18(i64 %a18, i64 %b18) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vcmpy.s0.sat.i(i64 %a18, i64 %b18)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vcmpy.s0.sat.i(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpywouh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat
+
+define void @test19(i64 %a19, i64 %b19) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyuh.s0(i64 %a19, i64 %b19)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyuh.s0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vabsdiffh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test20(i64 %a20, i64 %b20) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vabsdiffh(i64 %a20, i64 %b20)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vabsdiffh(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrcmpyr(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}*)
+
+define void @test21(i64 %a21, i64 %b21) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vrcmpyr.s0c(i64 %a21, i64 %b21)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vrcmpyr.s0c(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpyweuh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):rnd:sat
+
+define void @test22(i64 %a22, i64 %b22) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyul.rs0(i64 %a22, i64 %b22)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyul.rs0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpywouh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):rnd:sat
+
+define void @test23(i64 %a23, i64 %b23) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyuh.rs0(i64 %a23, i64 %b23)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyuh.rs0(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrmpybu(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test24(i64 %a24, i64 %b24) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M5.vrmpybuu(i64 %a24, i64 %b24)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M5.vrmpybuu(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vdmpy(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat
+
+define void @test25(i64 %a25, i64 %b25) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vdmpys.s1(i64 %a25, i64 %b25)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vdmpys.s1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat
+
+define void @test26(i64 %a26, i64 %b26) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyl.s1(i64 %a26, i64 %b26)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyl.s1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpyeh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat
+
+define void @test27(i64 %a27, i64 %b27) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vmpy2es.s1(i64 %a27, i64 %b27)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vmpy2es.s1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat
+
+define void @test28(i64 %a28, i64 %b28) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyh.s1(i64 %a28, i64 %b28)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyh.s1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1
+
+define void @test29(i64 %a29, i64 %b29) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M4.vrmpyoh.s1(i64 %a29, i64 %b29)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M4.vrmpyoh.s1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:rnd:sat
+
+define void @test30(i64 %a30, i64 %b30) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyl.rs1(i64 %a30, i64 %b30)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyl.rs1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vcmpyr(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat
+
+define void @test31(i64 %a31, i64 %b31) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vcmpy.s1.sat.r(i64 %a31, i64 %b31)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vcmpy.s1.sat.r(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:rnd:sat
+
+define void @test32(i64 %a32, i64 %b32) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyh.rs1(i64 %a32, i64 %b32)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyh.rs1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrmpybsu(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}})
+
+define void @test33(i64 %a33, i64 %b33) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M5.vrmpybsu(i64 %a33, i64 %b33)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M5.vrmpybsu(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vrmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1
+
+define void @test34(i64 %a34, i64 %b34) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M4.vrmpyeh.s1(i64 %a34, i64 %b34)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M4.vrmpyeh.s1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpyweuh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat
+
+define void @test35(i64 %a35, i64 %b35) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyul.s1(i64 %a35, i64 %b35)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyul.s1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vcmpyi(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat
+
+define void @test36(i64 %a36, i64 %b36) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.vcmpy.s1.sat.i(i64 %a36, i64 %b36)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.vcmpy.s1.sat.i(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpywouh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat
+
+define void @test37(i64 %a37, i64 %b37) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyuh.s1(i64 %a37, i64 %b37)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyuh.s1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpyweuh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:rnd:sat
+
+define void @test38(i64 %a38, i64 %b38) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyul.rs1(i64 %a38, i64 %b38)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyul.rs1(i64, i64) #1
+
+; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}vmpywouh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:rnd:sat
+
+define void @test39(i64 %a39, i64 %b39) #0 {
+entry:
+  %0 = tail call i64 @llvm.hexagon.M2.mmpyuh.rs1(i64 %a39, i64 %b39)
+  store i64 %0, i64* @c, align 8, !tbaa !1
+  ret void
+}
+
+declare i64 @llvm.hexagon.M2.mmpyuh.rs1(i64, i64) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.ident = !{!0}
+
+!0 = metadata !{metadata !"QuIC LLVM Hexagon Clang version 7.1-internal"}
+!1 = metadata !{metadata !2, metadata !2, i64 0}
+!2 = metadata !{metadata !"long long", metadata !3, i64 0}
+!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
+!4 = metadata !{metadata !"Simple C/C++ TBAA"}

test/MC/Hexagon/vector-mpy.s

+#REQUIRES: object-emission
+#This test will be enabled when assembler support has been added.
+
+#RUN: llvm-mc -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+
+# Check encoding bits for vector multiply instructions.
+
+r7:6=vrmpywoh(r13:12,r7:6)
+#CHECK: e82cc646 { r7:6 = vrmpywoh(r13:12, r7:6) }
+
+r5:4=vrmpywoh(r1:0,r1:0):<<1
+#CHECK: e8a0c044 { r5:4 = vrmpywoh(r1:0, r1:0):<<1 }
+
+r17:16=vrmpyweh(r1:0,r25:24)
+#CHECK: e840d890 { r17:16 = vrmpyweh(r1:0, r25:24) }
+
+r9:8=vrmpyweh(r1:0,r21:20):<<1
+#CHECK: e8c0d488 { r9:8 = vrmpyweh(r1:0, r21:20):<<1 }
+
+r5:4=vmpyweuh(r1:0,r3:2):rnd:sat
+#CHECK: e860c2a4 { r5:4 = vmpyweuh(r1:0, r3:2):rnd:sat }
+
+r29:28=vmpyweuh(lr:fp,r9:8):<<1:rnd:sat
+#CHECK: e8fec8bc { r29:28 = vmpyweuh(r31:30, r9:8):<<1:rnd:sat }
+
+r13:12=vmpyweuh(lr:fp,r31:30):sat
+#CHECK: e85edeac { r13:12 = vmpyweuh(r31:30, r31:30):sat }
+
+r19:18=vmpyweuh(r17:16,r17:16):<<1:sat
+#CHECK: e8d0d0b2 { r19:18 = vmpyweuh(r17:16, r17:16):<<1:sat }
+
+r25:24=vraddub(r15:14,r3:2)
+#CHECK: e84ec238 { r25:24 = vraddub(r15:14, r3:2) }
+
+r7:6=vrsadub(r27:26,r23:22)
+#CHECK: e85ad646 { r7:6 = vrsadub(r27:26, r23:22) }
+
+r9:8=vrmpywoh(r13:12,r1:0)
+#CHECK: e82cc048 { r9:8 = vrmpywoh(r13:12, r1:0) }
+
+r5:4=vrmpyweh(r25:24,r17:16):<<1
+#CHECK: e8d8d084 { r5:4 = vrmpyweh(r25:24, r17:16):<<1 }
+
+r3:2=vabsdiffw(r19:18,r5:4)
+#CHECK: e824d202 { r3:2 = vabsdiffw(r19:18, r5:4) }
+
+r27:26=vabsdiffh(lr:fp,r13:12)
+#CHECK: e86cde1a { r27:26 = vabsdiffh(r31:30, r13:12) }
+
+r31:30=vrcmpyi(r27:26,r23:22*)
+#CHECK: e85ad61e { r31:30 = vrcmpyi(r27:26, r23:22*) }
+
+r15:14=vrcmpyi(r15:14,r23:22)
+#CHECK: e80ed60e { r15:14 = vrcmpyi(r15:14, r23:22) }
+
+r3:2=vrcmpyr(r5:4,r17:16*)
+#CHECK: e864d022 { r3:2 = vrcmpyr(r5:4, r17:16*) }
+
+lr:fp=vrcmpyr(r7:6,r19:18)
+#CHECK: e806d23e { r31:30 = vrcmpyr(r7:6, r19:18) }
+
+r9:8=vrmpyweh(r15:14,r5:4)
+#CHECK: e84ec488 { r9:8 = vrmpyweh(r15:14, r5:4) }
+
+r11:10=vrmpyh(r3:2,r29:28)
+#CHECK: e802dc4a { r11:10 = vrmpyh(r3:2, r29:28) }
+
+r5:4=vmpywoh(r3:2,lr:fp):<<1:sat
+#CHECK: e882dee4 { r5:4 = vmpywoh(r3:2, r31:30):<<1:sat }
+
+r5:4=vmpywoh(r25:24,r5:4):sat
+#CHECK: e818c4e4 { r5:4 = vmpywoh(r25:24, r5:4):sat }
+
+r13:12=vmpyeh(r3:2,r3:2):sat
+#CHECK: e802c2cc { r13:12 = vmpyeh(r3:2, r3:2):sat }
+
+r15:14=vmpyeh(r11:10,r19:18):<<1:sat
+#CHECK: e88ad2ce { r15:14 = vmpyeh(r11:10, r19:18):<<1:sat }
+
+r13:12=vdmpy(r1:0,r21:20):sat
+#CHECK: e800d48c { r13:12 = vdmpy(r1:0, r21:20):sat }
+
+r11:10=vdmpy(r3:2,r23:22):<<1:sat
+#CHECK: e882d68a { r11:10 = vdmpy(r3:2, r23:22):<<1:sat }
+
+r11:10=vcmpyr(r17:16,r15:14):sat
+#CHECK: e830ceca { r11:10 = vcmpyr(r17:16, r15:14):sat }
+
+r31:30=vcmpyr(r17:16,r21:20):<<1:sat
+#CHECK: e8b0d4de { r31:30 = vcmpyr(r17:16, r21:20):<<1:sat }
+
+r11:10=vcmpyi(r25:24,r15:14):sat
+#CHECK: e858ceca { r11:10 = vcmpyi(r25:24, r15:14):sat }
+
+r23:22=vcmpyi(r17:16,r11:10):<<1:sat
+#CHECK: e8d0cad6 { r23:22 = vcmpyi(r17:16, r11:10):<<1:sat }
+
+lr:fp=vrmpywoh(r19:18,r17:16):<<1
+#CHECK: e8b2d05e { r31:30 = vrmpywoh(r19:18, r17:16):<<1 }
+
+r25:24=vrmpybsu(r29:28,r19:18)
+#CHECK: e8dcd238 { r25:24 = vrmpybsu(r29:28, r19:18) }
+
+r19:18=vrmpybu(r23:22,r9:8)
+#CHECK: e896c832 { r19:18 = vrmpybu(r23:22, r9:8) }
+
+r19:18=vmpyweh(r13:12,r3:2):<<1:sat
+#CHECK: e88cc2b2 { r19:18 = vmpyweh(r13:12, r3:2):<<1:sat }
+
+r25:24=vmpyweh(r29:28,r7:6):sat
+#CHECK: e81cc6b8 { r25:24 = vmpyweh(r29:28, r7:6):sat }
+
+r15:14=vmpywoh(r27:26,r23:22):<<1:rnd:sat
+#CHECK: e8bad6ee { r15:14 = vmpywoh(r27:26, r23:22):<<1:rnd:sat }
+
+r25:24=vmpywoh(r15:14,r31:30):rnd:sat
+#CHECK: e82edef8 { r25:24 = vmpywoh(r15:14, r31:30):rnd:sat }
+
+r27:26=vmpywouh(r13:12,r3:2):<<1:sat
+#CHECK: e8ccc2fa { r27:26 = vmpywouh(r13:12, r3:2):<<1:sat }
+
+r11:10=vmpywouh(r31:30,r13:12):sat
+#CHECK: e85eccea { r11:10 = vmpywouh(r31:30, r13:12):sat }
+
+lr:fp=vmpyweh(r19:18,r27:26):<<1:rnd:sat
+#CHECK: e8b2dabe { r31:30 = vmpyweh(r19:18, r27:26):<<1:rnd:sat }
+
+r29:28=vmpyweh(r9:8,r19:18):rnd:sat
+#CHECK: e828d2bc { r29:28 = vmpyweh(r9:8, r19:18):rnd:sat }
+
+r11:10=vmpywouh(r1:0,r15:14):<<1:rnd:sat
+#CHECK: e8e0ceea { r11:10 = vmpywouh(r1:0, r15:14):<<1:rnd:sat }
+
+r9:8=vmpywouh(r15:14,lr:fp):rnd:sat
+#CHECK: e86edee8 { r9:8 = vmpywouh(r15:14, r31:30):rnd:sat }