[X86] [ASM INTEL SYNTAX] fix for incorrect assembler code generation when x86-asm-syntax=intel (PR34617)

[kbelochapka]

Summary

fix for incorrect code generation when x86-asm-syntax=intel

[craig.topper]

LGTM

[coby]

suggested change will work fine if one is to solely consider masm / gas, as llvm's (x86) integrated assembler is yet to be introduced to the 'offset' keyword (handle it partially and falsely as part of inline-asm only).
for example, the following (dumb) snippet:

void *f() {
  return "";
}

under clang -cc1 -S -mllvm -x86-asm-syntax=intel -mrelocation-model static will produce the following asm (amongst other boilerplate):

movabs  rax, offset .L.str

which in turn, under clang -cc1as will yield:

error: cannot use more than one symbol in memory operand

see D37461 for a comprehensive proposal, which answers PR34617 as well

lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp

void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                        raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     printRegName(O, Op.getReg());
   } else if (Op.isImm()) {
     O << formatImm((int64_t)Op.getImm());
   } else {
     assert(Op.isExpr() && "unknown operand kind in printOperand");
+    O << "offset ";
     Op.getExpr()->print(O, &MAI);
   }
 }
 
 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
                                             raw_ostream &O) {
   const MCOperand &BaseReg  = MI->getOperand(Op+X86::AddrBaseReg);
   unsigned ScaleVal         = MI->getOperand(Op+X86::AddrScaleAmt).getImm();

test/MC/X86/intel-syntax-var-offset.ll

+;RUN: llc -mtriple=x86_64-unknown-unknown -filetype=asm -x86-asm-syntax=intel < %s | FileCheck %s --check-prefix=CHECK
+;PR34617
+
+;Compile it with: "clang -O1 -emit-llvm"
+;char X[4];
+;volatile char* PX;
+;char Y[4];
+;volatile char* PY;
+;char Z[4];
+;volatile char* PZ;
+;char* test057(long long x) {
+;        asm ("movq %1, %%rax;"
+;             "movq %%rax, %0;"
+;             "pushq $Y;"
+;             "popq %%rcx;"
+;             "movq %%rcx, PY;"
+;             "movq $X, %%rdx;"
+;             "movq %%rdx, PX;"
+;             :"=r"(PZ)
+;             :"p"(Z)
+;             :"%rax", "%rcx", "%rdx"
+;             );
+;    return (char*)PZ;
+;}
+
+; CHECK:  mov rax, offset Z
+; CHECK:  push  offset Y
+; CHECK:  pop rcx
+; CHECK:  mov qword ptr [PY], rcx
+; CHECK:  mov rdx, offset X
+; CHECK:  mov qword ptr [PX], rdx
+
+@PZ = common global i8* null, align 8
+@Z = common global [4 x i8] zeroinitializer, align 1
+@X = common global [4 x i8] zeroinitializer, align 1
+@PX = common global i8* null, align 8
+@Y = common global [4 x i8] zeroinitializer, align 1
+@PY = common global i8* null, align 8
+
+define i8* @test057(i64 %x) {
+entry:
+  %x.addr = alloca i64, align 8
+  store i64 %x, i64* %x.addr, align 8
+  %0 = call i8* asm "movq $1, %rax;movq %rax, $0;pushq $$Y;popq %rcx;movq %rcx, PY;movq $$X, %rdx;movq %rdx, PX;", "=r,im,~{rax},~{rcx},~{rdx},~{dirflag},~{fpsr},~{flags}"(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @Z, i32 0, i32 0))
+  store i8* %0, i8** @PZ, align 8
+  %1 = load i8*, i8** @PZ, align 8
+  ret i8* %1
+}
+