[ARM64] Add condition code operand type such that proper diagnostics can be emitted

[bsmith]

Summary

This patch adds a condition code operand type in the AsmParser, such that incorrect conditions can be properly diagnosed.

As with my previous patches, there is no testcase for this as it is part of the merge of MC/AArch64/basic-a64-diagnostics.s.

[t.p.northover]

Hi Bradley,

I think this looks good too.

Tim.

lib/Target/ARM64/ARM64InstrFormats.td

 }
 
 // 8-bit floating-point immediate encodings.
 def FPImmOperand : AsmOperandClass {
   let Name = "FPImm";
   let ParserMethod = "tryParseFPImm";
 }
 
+def CondCode : AsmOperandClass {
+  let Name = "CondCode";
+  let DiagnosticType = "InvalidCondCode";
+}
+
 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
 // are encoded as the eight bit value 'abcdefgh'.
 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
 
 
 //===----------------------------------------------------------------------===//
 // Operand Definitions.

 class SpecialReturn<bits<4> opc, string asm>
     : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
   let Inst{9-5} = 0b11111;
 }
 
 //---
 // Conditional branch instruction.
 //---
-// Branch condition code.
-// 4-bit immediate. Pretty-printed as .<cc>
-def dotCcode : Operand<i32> {
-  let PrintMethod = "printDotCondCode";
+
+// Condition code.
+// 4-bit immediate. Pretty-printed as <cc>
+def ccode : Operand<i32> {
+  let PrintMethod = "printCondCode";
+  let ParserMatchClass = CondCode;
+}
+def inv_ccode : Operand<i32> {
+  let PrintMethod = "printInverseCondCode";
+  let ParserMatchClass = CondCode;
 }
 
 // Conditional branch target. 19-bit immediate. The low two bits of the target
 // offset are implied zero and so are not part of the immediate.
 def PCRelLabel19Operand : AsmOperandClass {
   let Name = "PCRelLabel19";
   let DiagnosticType = "InvalidLabel";
 }
 def am_brcond : Operand<OtherVT> {
   let EncoderMethod = "getCondBranchTargetOpValue";
   let DecoderMethod = "DecodePCRelLabel19";
   let PrintMethod = "printAlignedLabel";
   let ParserMatchClass = PCRelLabel19Operand;
 }
 
-class BranchCond : I<(outs), (ins dotCcode:$cond, am_brcond:$target),
-                     "b", "$cond\t$target", "",
+class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target),
+                     "b", ".$cond\t$target", "",
                      [(ARM64brcond bb:$target, imm:$cond, NZCV)]>,
                    Sched<[WriteBr]> {
   let isBranch = 1;
   let isTerminator = 1;
   let Uses = [NZCV];
 
   bits<4> cond;
   bits<19> target;
class TestBranch<bit op, string asm, SDNode node>
   let DecoderMethod = "DecodeTestAndBranch";
 }
 
 //---
 // Unconditional branch (immediate) instructions.
 //---
 def BranchTarget26Operand : AsmOperandClass {
   let Name = "BranchTarget26";
+  let DiagnosticType = "InvalidLabel";
 }
 def am_b_target : Operand<OtherVT> {
   let EncoderMethod = "getBranchTargetOpValue";
   let PrintMethod = "printAlignedLabel";
   let ParserMatchClass = BranchTarget26Operand;
 }
 def am_bl_target : Operand<i64> {
   let EncoderMethod = "getBranchTargetOpValue";
multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
   def : LogicalRegAlias<mnemonic,
                         !cast<Instruction>(NAME#"Xrs"), GPR64>;
 }
 
 //---
 // Conditionally set flags
 //---
 
-// Condition code.
-// 4-bit immediate. Pretty-printed as <cc>
-def ccode : Operand<i32> {
-  let PrintMethod = "printCondCode";
-}
-
-def inv_ccode : Operand<i32> {
-  let PrintMethod = "printInverseCondCode";
-}
-
 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
 class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
     : I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
          asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
       Sched<[WriteI]> {
   let Uses = [NZCV];
   let Defs = [NZCV];
 

lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp

private:
   MCAsmParser &Parser;
 
   MCAsmParser &getParser() const { return Parser; }
   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
 
   SMLoc getLoc() const { return Parser.getTok().getLoc(); }
 
   bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
-  unsigned parseCondCodeString(StringRef Cond);
+  ARM64CC::CondCode parseCondCodeString(StringRef Cond);
   bool parseCondCode(OperandVector &Operands, bool invertCondCode);
   int tryParseRegister();
   int tryMatchVectorRegister(StringRef &Kind, bool expected);
   bool parseRegister(OperandVector &Operands);
   bool parseMemory(OperandVector &Operands);
   bool parseSymbolicImmVal(const MCExpr *&ImmVal);
   bool parseVectorList(OperandVector &Operands);
   bool parseOperand(OperandVector &Operands, bool isCondCode,
enum MemIdxKindTy {
     ImmediateOffset, // pre-indexed, no writeback
     RegisterOffset   // register offset, with optional extend
   };
 
 private:
   enum KindTy {
     k_Immediate,
     k_ShiftedImm,
+    k_CondCode,
     k_Memory,
     k_Register,
     k_VectorList,
     k_VectorIndex,
     k_Token,
     k_SysReg,
     k_SysCR,
     k_Prefetch,
struct ImmOp {
     const MCExpr *Val;
   };
 
   struct ShiftedImmOp {
     const MCExpr *Val;
     unsigned ShiftAmount;
   };
 
+  struct CondCodeOp {
+    ARM64CC::CondCode Code;
+  };
+
   struct FPImmOp {
     unsigned Val; // Encoded 8-bit representation.
   };
 
   struct BarrierOp {
     unsigned Val; // Not the enum since not all values have names.
   };
 
private:
 
   union {
     struct TokOp Tok;
     struct RegOp Reg;
     struct VectorListOp VectorList;
     struct VectorIndexOp VectorIndex;
     struct ImmOp Imm;
     struct ShiftedImmOp ShiftedImm;
+    struct CondCodeOp CondCode;
     struct FPImmOp FPImm;
     struct BarrierOp Barrier;
     struct SysRegOp SysReg;
     struct SysCRImmOp SysCRImm;
     struct PrefetchOp Prefetch;
     struct ShiftExtendOp ShiftExtend;
     struct MemOp Mem;
   };
case k_Token:
       Tok = o.Tok;
       break;
     case k_Immediate:
       Imm = o.Imm;
       break;
     case k_ShiftedImm:
       ShiftedImm = o.ShiftedImm;
       break;
+    case k_CondCode:
+      CondCode = o.CondCode;
+      break;
     case k_FPImm:
       FPImm = o.FPImm;
       break;
     case k_Barrier:
       Barrier = o.Barrier;
       break;
     case k_Register:
       Reg = o.Reg;
const MCExpr *getShiftedImmVal() const {
     return ShiftedImm.Val;
   }
 
   unsigned getShiftedImmShift() const {
     assert(Kind == k_ShiftedImm && "Invalid access!");
     return ShiftedImm.ShiftAmount;
   }
 
+  ARM64CC::CondCode getCondCode() const {
+    assert(Kind == k_CondCode && "Invalid access!");
+    return CondCode.Code;
+  }
+
   unsigned getFPImm() const {
     assert(Kind == k_FPImm && "Invalid access!");
     return FPImm.Val;
   }
 
   unsigned getBarrier() const {
     assert(Kind == k_Barrier && "Invalid access!");
     return Barrier.Val;
if (ARM64AsmParser::classifySymbolRef(Expr, ELFRefKind,
           || ELFRefKind == ARM64MCExpr::VK_TPREL_LO12_NC
           || ELFRefKind == ARM64MCExpr::VK_TLSDESC_LO12;
     }
 
     // Otherwise it should be a real immediate in range:
     const MCConstantExpr *CE = cast<MCConstantExpr>(Expr);
     return CE->getValue() >= 0 && CE->getValue() <= 0xfff;
   }
+  bool isCondCode() const { return Kind == k_CondCode; }
   bool isSIMDImmType10() const {
     if (!isImm())
       return false;
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
     if (!MCE)
       return false;
     return ARM64_AM::isAdvSIMDModImmType10(MCE->getValue());
   }
if (isShiftedImm()) {
       addExpr(Inst, getShiftedImmVal());
       Inst.addOperand(MCOperand::CreateImm(getShiftedImmShift()));
     } else {
       addExpr(Inst, getImm());
       Inst.addOperand(MCOperand::CreateImm(0));
     }
   }
 
+  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::CreateImm(getCondCode()));
+  }
+
   void addAdrpLabelOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
     if (!MCE)
       addExpr(Inst, getImm());
     else
       Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 12));
   }
static ARM64Operand *CreateShiftedImm(const MCExpr *Val, unsigned ShiftAmount,
     ARM64Operand *Op = new ARM64Operand(k_ShiftedImm, Ctx);
     Op->ShiftedImm .Val = Val;
     Op->ShiftedImm.ShiftAmount = ShiftAmount;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
+  static ARM64Operand *CreateCondCode(ARM64CC::CondCode Code, SMLoc S, SMLoc E,
+                                      MCContext &Ctx) {
+    ARM64Operand *Op = new ARM64Operand(k_CondCode, Ctx);
+    Op->CondCode.Code = Code;
+    Op->StartLoc = S;
+    Op->EndLoc = E;
+    return Op;
+  }
+
   static ARM64Operand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
     ARM64Operand *Op = new ARM64Operand(k_FPImm, Ctx);
     Op->FPImm.Val = Val;
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;
   }
 
case k_Immediate:
     break;
   case k_ShiftedImm: {
     unsigned Shift = getShiftedImmShift();
     OS << "<shiftedimm ";
     getShiftedImmVal()->print(OS);
     OS << ", lsl #" << ARM64_AM::getShiftValue(Shift) << ">";
     break;
   }
+  case k_CondCode:
+    OS << "<condcode " << getCondCode() << ">";
+    break;
   case k_Memory:
     OS << "<memory>";
     break;
   case k_Register:
     OS << "<register " << getReg() << ">";
     break;
   case k_VectorList: {
     OS << "<vectorlist ";
ARM64AsmParser::tryParseAddSubImm(OperandVector &Operands) {
 
   SMLoc E = Parser.getTok().getLoc();
   Operands.push_back(ARM64Operand::CreateShiftedImm(Imm, ShiftAmount,
                                                     S, E, getContext()));
   return MatchOperand_Success;
 }
 
 /// parseCondCodeString - Parse a Condition Code string.
-unsigned ARM64AsmParser::parseCondCodeString(StringRef Cond) {
-  unsigned CC = StringSwitch<unsigned>(Cond.lower())
+ARM64CC::CondCode ARM64AsmParser::parseCondCodeString(StringRef Cond) {
+  ARM64CC::CondCode CC = StringSwitch<ARM64CC::CondCode>(Cond.lower())
                     .Case("eq", ARM64CC::EQ)
                     .Case("ne", ARM64CC::NE)
                     .Case("cs", ARM64CC::HS)
                     .Case("hs", ARM64CC::HS)
                     .Case("cc", ARM64CC::LO)
                     .Case("lo", ARM64CC::LO)
                     .Case("mi", ARM64CC::MI)
                     .Case("pl", ARM64CC::PL)

 /// parseCondCode - Parse a Condition Code operand.
 bool ARM64AsmParser::parseCondCode(OperandVector &Operands,
                                    bool invertCondCode) {
   SMLoc S = getLoc();
   const AsmToken &Tok = Parser.getTok();
   assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
 
   StringRef Cond = Tok.getString();
-  unsigned CC = parseCondCodeString(Cond);
+  ARM64CC::CondCode CC = parseCondCodeString(Cond);
   if (CC == ARM64CC::Invalid)
     return TokError("invalid condition code");
   Parser.Lex(); // Eat identifier token.
 
   if (invertCondCode)
     CC = ARM64CC::getInvertedCondCode(ARM64CC::CondCode(CC));
 
-  const MCExpr *CCExpr = MCConstantExpr::Create(CC, getContext());
   Operands.push_back(
-      ARM64Operand::CreateImm(CCExpr, S, getLoc(), getContext()));
+      ARM64Operand::CreateCondCode(CC, S, getLoc(), getContext()));
   return false;
 }
 
 /// tryParseOptionalShift - Some operands take an optional shift argument. Parse
 /// them if present.
 ARM64AsmParser::OperandMatchResultTy
 ARM64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
   const AsmToken &Tok = Parser.getTok();
bool ARM64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
   // Handle condition codes for a branch mnemonic
   if (Head == "b" && Next != StringRef::npos) {
     Start = Next;
     Next = Name.find('.', Start + 1);
     Head = Name.slice(Start + 1, Next);
 
     SMLoc SuffixLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
                                             (Head.data() - Name.data()));
-    unsigned CC = parseCondCodeString(Head);
+    ARM64CC::CondCode CC = parseCondCodeString(Head);
     if (CC == ARM64CC::Invalid)
       return Error(SuffixLoc, "invalid condition code");
-    const MCExpr *CCExpr = MCConstantExpr::Create(CC, getContext());
     Operands.push_back(
-        ARM64Operand::CreateImm(CCExpr, NameLoc, NameLoc, getContext()));
+        ARM64Operand::CreateToken(".", true, SuffixLoc, getContext()));
+    Operands.push_back(
+        ARM64Operand::CreateCondCode(CC, NameLoc, NameLoc, getContext()));
   }
 
   // Add the remaining tokens in the mnemonic.
   while (Next != StringRef::npos) {
     Start = Next;
     Next = Name.find('.', Start + 1);
     Head = Name.slice(Start, Next);
     SMLoc SuffixLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
bool ARM64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode) {
   switch (ErrCode) {
   case Match_MissingFeature:
     return Error(Loc,
                  "instruction requires a CPU feature not currently enabled");
   case Match_InvalidOperand:
     return Error(Loc, "invalid operand for instruction");
   case Match_InvalidSuffix:
     return Error(Loc, "invalid type suffix for instruction");
+  case Match_InvalidCondCode:
+    return Error(Loc, "expected AArch64 condition code");
   case Match_AddSubRegExtendSmall:
     return Error(Loc,
       "expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4]");
   case Match_AddSubRegExtendLarge:
     return Error(Loc,
       "expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]");
   case Match_AddSubSecondSource:
     return Error(Loc,
bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidMemoryIndexed64:
   case Match_InvalidMemoryIndexed128:
     // If there is a '!' after the memory operand that failed, we really
     // want the diagnostic for the pre-indexed instruction variant instead.
     if (Operands.size() > ErrorInfo + 1 &&
         ((ARM64Operand *)Operands[ErrorInfo + 1])->isTokenEqual("!"))
       MatchResult = Match_InvalidMemoryIndexedSImm9;
   // FALL THROUGH
+  case Match_InvalidCondCode:
   case Match_AddSubRegExtendSmall:
   case Match_AddSubRegExtendLarge:
   case Match_AddSubSecondSource:
   case Match_LogicalSecondSource:
   case Match_AddSubRegShift32:
   case Match_AddSubRegShift64:
   case Match_InvalidMovImm32Shift:
   case Match_InvalidMovImm64Shift:

lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h

protected:
   void printLogicalImm32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printLogicalImm64(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printShifter(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printShiftedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printInverseCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
-  void printDotCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printAlignedLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printAMIndexed(const MCInst *MI, unsigned OpNum, unsigned Scale,
                       raw_ostream &O);
   void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
                         raw_ostream &O);
 
   template<int BitWidth>
   void printAMIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O) {

lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp

if ( ((Dest == ARM64::SP || Src1 == ARM64::SP) &&
       return;
     }
   }
   O << ", " << ARM64_AM::getShiftExtendName(ExtType);
   if (ShiftVal != 0)
     O << " #" << ShiftVal;
 }
 
-void ARM64InstPrinter::printDotCondCode(const MCInst *MI, unsigned OpNum,
-                                        raw_ostream &O) {
-  ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
-  O << '.' << ARM64CC::getCondCodeName(CC);
-}
-
 void ARM64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
                                      raw_ostream &O) {
   ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
   O << ARM64CC::getCondCodeName(CC);
 }
 
 void ARM64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
                                             raw_ostream &O) {