[mips] Implement l[wd]c3, and s[wd]c3.

[dsanders]

Summary

These instructions were added in MIPS-I, and MIPS-II but were removed in
MIPS-III. Interestingly, GAS continues to accept them when assembling for
MIPS-III.

For the moment, these instructions will follow GAS and accept them for
MIPS-III and newer but this will be tightened up when the invalid-*.s
tests are added.

Depends on D3647

[vmedic]

LGTM

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

enum RegKind {
     RegKind_FCC = 4,      /// FCC
     RegKind_MSA128 = 8,   /// MSA128[BHWD] (makes no difference which)
     RegKind_MSACtrl = 16, /// MSA control registers
     RegKind_COP2 = 32,    /// COP2
     RegKind_ACC = 64,     /// HI32DSP, LO32DSP, and ACC64DSP (depending on
                           /// context).
     RegKind_CCR = 128,    /// CCR
     RegKind_HWRegs = 256, /// HWRegs
+    RegKind_COP3 = 512,   /// COP3
 
     /// Potentially any (e.g. $1)
     RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
                       RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
-                      RegKind_CCR | RegKind_HWRegs
+                      RegKind_CCR | RegKind_HWRegs | RegKind_COP3
   };
 
 private:
   enum KindTy {
     k_Immediate,     /// An immediate (possibly involving symbol references)
     k_Memory,        /// Base + Offset Memory Address
     k_PhysRegister,  /// A physical register from the Mips namespace
     k_RegisterIndex, /// A register index in one or more RegKind.
private:
   /// Coerce the register to COP2 and return the real register for the
   /// current target.
   unsigned getCOP2Reg() const {
     assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
     unsigned ClassID = Mips::COP2RegClassID;
     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
   }
 
+  /// Coerce the register to COP3 and return the real register for the
+  /// current target.
+  unsigned getCOP3Reg() const {
+    assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
+    unsigned ClassID = Mips::COP3RegClassID;
+    return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
+  }
+
   /// Coerce the register to ACC64DSP and return the real register for the
   /// current target.
   unsigned getACC64DSPReg() const {
     assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
     unsigned ClassID = Mips::ACC64DSPRegClassID;
     return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
   }
 
void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
     Inst.addOperand(MCOperand::CreateReg(getMSACtrlReg()));
   }
 
   void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateReg(getCOP2Reg()));
   }
 
+  void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::CreateReg(getCOP3Reg()));
+  }
+
   void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateReg(getACC64DSPReg()));
   }
 
   void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateReg(getHI32DSPReg()));
bool isFCCAsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_FCC && RegIdx.Index <= 7;
   }
   bool isACCAsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
   }
   bool isCOP2AsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
   }
+  bool isCOP3AsmReg() const {
+    return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
+  }
   bool isMSA128AsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
   }
   bool isMSACtrlAsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
   }
 
   /// getStartLoc - Get the location of the first token of this operand.

lib/Target/Mips/MipsInstrFPU.td

def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2,
                FGR_64;
 }
 
 def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>,
            ISA_MIPS2, FGR_32;
 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
            ISA_MIPS2, FGR_32;
 
-/// Cop2 Memory Instructions
+// Cop2 Memory Instructions
+// FIXME: These aren't really FPU instructions and as such don't belong in this
+//        file
 def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>;
 def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>;
 def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>, ISA_MIPS2;
 def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, ISA_MIPS2;
 
+// Cop3 Memory Instructions
+// FIXME: These aren't really FPU instructions and as such don't belong in this
+//        file
+def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
+def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
+def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>, ISA_MIPS2;
+def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, ISA_MIPS2;
+
 // Indexed loads and stores.
 // Base register + offset register addressing mode (indicated by "x" in the
 // instruction mnemonic) is disallowed under NaCl.
 let AdditionalPredicates = [IsNotNaCl, HasFPIdx] in {
   def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>;
   def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>;
 }
 

lib/Target/Mips/MipsRegisterInfo.td

let Namespace = "Mips" in {
   // FP condition code registers.
   foreach I = 0-7 in
   def FCC#I : MipsReg<#I, "fcc"#I>;
 
   // COP2 registers.
   foreach I = 0-31 in
   def COP2#I : MipsReg<#I, ""#I>;
 
+  // COP3 registers.
+  foreach I = 0-31 in
+  def COP3#I : MipsReg<#I, ""#I>;
+
   // PC register
   def PC : Register<"pc">;
 
   // Hardware register $29
   foreach I = 0-31 in
   def HWR#I : MipsReg<#I, ""#I>;
 
   // Accum registers

 }
 
 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
 
 // Coprocessor 2 registers.
 def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
            Unallocatable;
 
+// Coprocessor 3 registers.
+def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>,
+           Unallocatable;
+
 // Octeon multiplier and product registers
 def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>,
                  Unallocatable;
 def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>,
                Unallocatable;
 
 // Register Operands.
 

 def HWRegsAsmOperand : MipsAsmRegOperand {
   let Name = "HWRegsAsmReg";
 }
 
 def COP2AsmOperand : MipsAsmRegOperand {
   let Name = "COP2AsmReg";
 }
 
+def COP3AsmOperand : MipsAsmRegOperand {
+  let Name = "COP3AsmReg";
+}
+
 def HWRegsOpnd : RegisterOperand<HWRegs> {
   let ParserMatchClass = HWRegsAsmOperand;
 }
 
 def AFGR64Opnd : RegisterOperand<AFGR64> {
   let ParserMatchClass = AFGR64AsmOperand;
 }
 

 def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
   let ParserMatchClass = ACC64DSPAsmOperand;
 }
 
 def COP2Opnd : RegisterOperand<COP2> {
   let ParserMatchClass = COP2AsmOperand;
 }
 
+def COP3Opnd : RegisterOperand<COP3> {
+  let ParserMatchClass = COP3AsmOperand;
+}
+
 def MSA128BOpnd : RegisterOperand<MSA128B> {
   let ParserMatchClass = MSA128AsmOperand;
 }
 
 def MSA128HOpnd : RegisterOperand<MSA128H> {
   let ParserMatchClass = MSA128AsmOperand;
 }
 

test/MC/Mips/mips1/invalid-mips2-wrong-error.s

 # Instructions that are invalid and are correctly rejected but use the wrong
 # error message at the moment.
 #
 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \
 # RUN:     2>%t1
 # RUN: FileCheck %s < %t1
 
   .set noat
         ldc1      $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ldc2      $8,-21181($at)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        ldc3      $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         ll        $v0,-7321($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sc        $t7,18904($s3)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdc1      $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         sdc2      $20,23157($s2)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sdc3      $12,5835($t2)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/mips1/invalid-mips2.s

 # Instructions that are invalid
 #
 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \
 # RUN:     2>%t1
 # RUN: FileCheck %s < %t1
 
-  .set noat
+        .set noat
         ceil.w.d  $f11,$f25       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ceil.w.s  $f6,$f20        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         floor.w.d $f14,$f11       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         floor.w.s $f8,$f9         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.w.d $f6,$f4         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         round.w.s $f27,$f28       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         sqrt.d    $f17,$f22       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         sqrt.s    $f0,$f1         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         teqi      $s5,-17504      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         tgei      $s1,5025        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         tgeiu     $sp,-28621      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         tlti      $t6,-21059      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         tltiu     $ra,-5076       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         tnei      $t4,-29647      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         trunc.w.d $f22,$f15       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         trunc.w.s $f28,$f30       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips1/valid-xfail.s

 # Instructions that should be valid but currently fail for known reasons (e.g.
 # they aren't implemented yet).
 # This test is set up to XPASS if any instruction generates an encoding.
 #
 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | not FileCheck %s
 # CHECK-NOT: encoding
 # XFAIL: *
 
   .set noat
   lwc0  c0_entrylo,-7321($s2)
-  lwc3  $10,-32265($k0)
   swc0  c0_prid,18904($s3)

test/MC/Mips/mips1/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
   lbu $t0,30195($v1)
   lh  $t3,-8556($s5)
   lhu $s3,-22851($v0)
   li  $at,-29773
   li  $zero,-29889
   lw  $t0,5674($a1)
   lwc1  $f16,10225($k0)
   lwc2  $18,-841($a2)
+  lwc3  $10,-32265($k0)
   lwl $s4,-4231($t7)
   lwr $zero,-19147($gp)
   mfc1  $a3,$f27
   mfhi  $s3
   mfhi  $sp
   mflo  $s1
   mov.d $f20,$f14
   mov.s $f2,$f27
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s
   ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
   sub $s6,$s3,$t4
   sub.d $f18,$f3,$f17
   sub.s $f23,$f22,$f22
   subu  $sp,$s6,$s6
   sw  $ra,-10160($sp)
   swc1  $f6,-8465($t8)
   swc2  $25,24880($s0)
+  swc3  $10,-32265($k0)
   swl $t7,13694($s3)
   swr $s1,-26590($t6)
   tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
   tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
   tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
   tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
   xor $s2,$a0,$s8

test/MC/Mips/mips2/valid-xfail.s

-# Instructions that should be valid but currently fail for known reasons (e.g.
-# they aren't implemented yet).
-# This test is set up to XPASS if any instruction generates an encoding.
-#
-# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | not FileCheck %s
-# CHECK-NOT: encoding
-# XFAIL: *
-
-  .set noat
-  ldc3  $29,-28645($s1)
-  lwc3  $10,-32265($k0)
-  sdc3  $12,5835($t2)

test/MC/Mips/mips2/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
   divu  $zero,$t9,$t7
   ehb                      # CHECK: ehb # encoding:  [0x00,0x00,0x00,0xc0]
   floor.w.d $f14,$f11
   floor.w.s $f8,$f9
   lb  $t8,-14515($t2)
   lbu $t0,30195($v1)
   ldc1  $f11,16391($s0)
   ldc2  $8,-21181($at)
+  ldc3  $29,-28645($s1)
   lh  $t3,-8556($s5)
   lhu $s3,-22851($v0)
   li  $at,-29773
   li  $zero,-29889
   ll  $v0,-7321($s2)
   lw  $t0,5674($a1)
   lwc1  $f16,10225($k0)
   lwc2  $18,-841($a2)
+  lwc3  $10,-32265($k0)
   lwl $s4,-4231($t7)
   lwr $zero,-19147($gp)
   mfc1  $a3,$f27
   mfhi  $s3
   mfhi  $sp
   mflo  $s1
   mov.d $f20,$f14
   mov.s $f2,$f27
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
   nor $a3,$zero,$a3
   or  $t4,$s0,$sp
   round.w.d $f6,$f4
   round.w.s $f27,$f28
   sb  $s6,-19857($t6)
   sc  $t7,18904($s3)
   sdc1  $f31,30574($t5)
   sdc2  $20,23157($s2)
+  sdc3  $12,5835($t2)
   sh  $t6,-6704($t7)
   sll   $a3,18               # CHECK: sll $7, $7, 18         # encoding: [0x00,0x07,0x3c,0x80]
   sll   $a3,$zero,18         # CHECK: sll $7, $zero, 18      # encoding: [0x00,0x00,0x3c,0x80]
   sll   $a3,$zero,$t1        # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
   sllv  $a3,$zero,$t1        # CHECK: sllv $7, $zero, $9     # encoding: [0x01,0x20,0x38,0x04]
   slt   $s7,$11,$k1          # CHECK: slt $23, $11, $27      # encoding: [0x01,0x7b,0xb8,0x2a]
   slti  $s1,$10,9489         # CHECK: slti $17, $10, 9489    # encoding: [0x29,0x51,0x25,0x11]
   sltiu $t9,$t9,-15531       # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s
   ssnop                      # CHECK: ssnop                  # encoding: [0x00,0x00,0x00,0x40]
   sub $s6,$s3,$t4
   sub.d $f18,$f3,$f17
   sub.s $f23,$f22,$f22
   subu  $sp,$s6,$s6
   sw  $ra,-10160($sp)
   swc1  $f6,-8465($t8)
   swc2  $25,24880($s0)
+  swc3  $10,-32265($k0)
   swl $t7,13694($s3)
   swr $s1,-26590($t6)
   teqi  $s5,-17504
   tgei  $s1,5025
   tgeiu $sp,-28621
   tlbp                       # CHECK: tlbp                   # encoding: [0x42,0x00,0x00,0x08]
   tlbr                       # CHECK: tlbr                   # encoding: [0x42,0x00,0x00,0x01]
   tlbwi                      # CHECK: tlbwi                  # encoding: [0x42,0x00,0x00,0x02]
   tlbwr                      # CHECK: tlbwr                  # encoding: [0x42,0x00,0x00,0x06]
   tlti  $t6,-21059
   tltiu $ra,-5076
   tnei  $t4,-29647
   trunc.w.d $f22,$f15
   trunc.w.s $f28,$f30
   xor $s2,$a0,$s8

test/MC/Mips/mips3/valid-xfail.s

-# Instructions that should be valid but currently fail for known reasons (e.g.
-# they aren't implemented yet).
-# This test is set up to XPASS if any instruction generates an encoding.
-#
-# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 | not FileCheck %s
-# CHECK-NOT: encoding
-# XFAIL: *
-
-  .set noat
-  lwc3  $10,-32265($k0)

test/MC/Mips/mips32/valid-xfail.s

# XFAIL: *
   c.ueq.d $fcc4,$f13,$f25
   c.ueq.s $fcc6,$f3,$f30
   c.ule.d $fcc7,$f25,$f18
   c.ule.s $fcc7,$f21,$f30
   c.ult.d $fcc6,$f6,$f17
   c.ult.s $fcc7,$f24,$f10
   c.un.d  $fcc6,$f23,$f24
   c.un.s  $fcc1,$f30,$f4
-  ldc3  $29,-28645($s1)
   rorv  $t5,$a3,$s5
-  sdc3  $12,5835($t2)

test/MC/Mips/mips32r2/valid-xfail.s

# XFAIL: *
   ftrunc_s.w  $w24,$w7
   ftrunc_u.d  $w20,$w25
   ftrunc_u.w  $w7,$w26
   insv  $s2,$at
   iret
   lbe $t6,122($t1)
   lbue  $t3,-108($t2)
   lbux  $t1,$t6($v0)
-  ldc3  $29,-28645($s1)
   lhe $s6,219($v1)
   lhue  $gp,118($t3)
   lhx $sp,$k0($t7)
   lle $gp,-237($ra)
   lwe $ra,-145($t6)
   lwle  $t3,-42($t3)
   lwre  $sp,-152($t8)
   lwx $t4,$t4($s4)
# XFAIL: *
   replv.qb  $t9,$t4
   rorv  $t5,$a3,$s5
   round.l.d $f12,$f1
   round.l.s $f25,$f5
   rsqrt.d $f3,$f28
   rsqrt.s $f4,$f8
   sbe $s7,33($s1)
   sce $sp,189($t2)
-  sdc3  $12,5835($t2)
   she $t8,105($v0)
   shilo $ac1,26
   shilov  $ac2,$t2
   shllv.ph  $t2,$s0,$s0
   shllv.qb  $gp,$v1,$zero
   shllv_s.ph  $k1,$at,$t5
   shllv_s.w $s1,$ra,$k0
   shrav.ph  $t9,$s2,$s1