[Mips] Fix for BBIT octeon instruction

[spetrovic]

Summary

This patch enables control flow optimization for variations of BBIT instruction. In this case optimization removes unnecessary branch after BBIT instruction.

Example:

void foo(long long var) {

		if ((var) & 0x2) {
			printf("\ntest");
		}

}

Without patch:

0000000000000000 <foo>:

 0:	67bdfff0 	daddiu	sp,sp,-16
 4:	ffbf0008 	sd	ra,8(sp)
 8:	ffbc0000 	sd	gp,0(sp)
 c:	3c010000 	lui	at,0x0
10:	c881000b 	bbit0	a0,0x1,40 <foo+0x40>
14:	0039102d 	daddu	v0,at,t9
18:	10000001 	b	20 <foo+0x20>
1c:	00000000 	nop
20:	645c0000 	daddiu	gp,v0,0
24:	df810000 	ld	at,0(gp)
28:	64240000 	daddiu	a0,at,0
2c:	3c010000 	lui	at,0x0
30:	003c082d 	daddu	at,at,gp
34:	dc390000 	ld	t9,0(at)
38:	0320f809 	jalr	t9
3c:	00000000 	nop
40:	dfbc0000 	ld	gp,0(sp)
44:	dfbf0008 	ld	ra,8(sp)
48:	03e00008 	jr	ra
4c:	67bd0010 	daddiu	sp,sp,16

With the patch:

0000000000000000 <foo>:

 0:	67bdfff0 	daddiu	sp,sp,-16
 4:	ffbf0008 	sd	ra,8(sp)
 8:	ffbc0000 	sd	gp,0(sp)
 c:	3c010000 	lui	at,0x0
10:	c8810009 	bbit0	a0,0x1,38 <foo+0x38>
14:	0039102d 	daddu	v0,at,t9
18:	645c0000 	daddiu	gp,v0,0
1c:	df810000 	ld	at,0(gp)
20:	64240000 	daddiu	a0,at,0
24:	3c010000 	lui	at,0x0
28:	003c082d 	daddu	at,at,gp
2c:	dc390000 	ld	t9,0(at)
30:	0320f809 	jalr	t9
34:	00000000 	nop
38:	dfbc0000 	ld	gp,0(sp)
3c:	dfbf0008 	ld	ra,8(sp)
40:	03e00008 	jr	ra
44:	67bd0010 	daddiu	sp,sp,16

[sdardis]

lib/Target/Mips/MipsSEInstrInfo.cpp

454–457 ↗

(On Diff #106433)

This looks incorrect. Shouldn't the opposite of bbit0 be bbit1?

[spetrovic]

lib/Target/Mips/MipsSEInstrInfo.cpp

454–457 ↗

(On Diff #106433)

Yes, my mistake.

[sdardis]

LGTM with some test fixes. My inlined comment about adding not test for 'j' and dropping the regexes applies to all the changes after the comment.

test/CodeGen/Mips/octeon.ll

95–96 ↗

(On Diff #106872)

You can drop the regexes for matching the basic block labels, as they're not matching anything.

96 ↗

(On Diff #106872)

Add 'OCTEON-NOT: j'

llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp

unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
   case Mips::BGEC64:   return Mips::BLTC64;
   case Mips::BGEUC64:  return Mips::BLTUC64;
   case Mips::BLTC64:   return Mips::BGEC64;
   case Mips::BLTUC64:  return Mips::BGEUC64;
   case Mips::BGTZC64:  return Mips::BLEZC64;
   case Mips::BGEZC64:  return Mips::BLTZC64;
   case Mips::BLTZC64:  return Mips::BGEZC64;
   case Mips::BLEZC64:  return Mips::BGTZC64;
+  case Mips::BBIT0:  return Mips::BBIT1;
+  case Mips::BBIT1:  return Mips::BBIT0;
+  case Mips::BBIT032:  return Mips::BBIT132;
+  case Mips::BBIT132:  return Mips::BBIT032;
   }
 }
 
 /// Adjust SP by Amount bytes.
 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
                                      MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I) const {
   MipsABIInfo ABI = Subtarget.getABI();
return (Opc == Mips::BEQ    || Opc == Mips::BEQ_MM || Opc == Mips::BNE    ||
           Opc == Mips::BNEC   || Opc == Mips::BLTC   || Opc == Mips::BGEC   ||
           Opc == Mips::BLTUC  || Opc == Mips::BGEUC  || Opc == Mips::BGTZC  ||
           Opc == Mips::BLEZC  || Opc == Mips::BGEZC  || Opc == Mips::BLTZC  ||
           Opc == Mips::BEQZC  || Opc == Mips::BNEZC  || Opc == Mips::BEQZC64 ||
           Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 ||
           Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
           Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
           Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
-          Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0;
+          Opc == Mips::BLEZC64 || Opc == Mips::BC || Opc == Mips::BBIT0 ||
+          Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
+          Opc == Mips::BBIT132) ? Opc : 0;
 }
 
 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator I) const {
 
   MachineInstrBuilder MIB;
   if (Subtarget.isGP64bit())
     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))

llvm/trunk/test/CodeGen/Mips/octeon.ll

 ; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON
 ; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64
+; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon -relocation-model=pic | FileCheck %s -check-prefixes=ALL,OCTEON-PIC
 
 define i64 @addi64(i64 %a, i64 %b) nounwind {
 entry:
 ; ALL-LABEL: addi64:
 ; OCTEON: jr      $ra
 ; OCTEON: baddu   $2, $4, $5
 ; MIPS64: daddu   $[[T0:[0-9]+]], $4, $5
 ; MIPS64: jr      $ra

 ; MIPS64: dsll   $[[T3:[0-9]+]], $[[T2]], 32
 ; MIPS64: jr     $ra
 ; MIPS64: dsrl   $2, $[[T3]], 32
   %res = icmp ne i64 %a, 42
   %res2 = zext i1 %res to i64
   ret i64 %res2
 }
 
-define i64 @bbit0(i64 %a) nounwind {
+define i64 @bbit1(i64 %a) nounwind {
 entry:
-; ALL-LABEL: bbit0:
-; OCTEON: bbit0   $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; ALL-LABEL: bbit1:
+; OCTEON: bbit1   $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; OCTEON-PIC-NOT: b  {{[[:space:]].*}}
+; OCTEON-NOT: j  {{[[:space:]].*}}
 ; MIPS64: andi  $[[T0:[0-9]+]], $4, 8
 ; MIPS64: bnez  $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]]
   %bit = and i64 %a, 8
   %res = icmp eq i64 %bit, 0
   br i1 %res, label %endif, label %if
 if:
   ret i64 48
 
 endif:
   ret i64 12
 }
 
-define i64 @bbit032(i64 %a) nounwind {
+define i64 @bbit132(i64 %a) nounwind {
 entry:
-; ALL-LABEL: bbit032:
-; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; ALL-LABEL: bbit132:
+; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; OCTEON-PIC-NOT: b  {{[[:space:]].*}}
+; OCTEON-NOT: j  {{[[:space:]].*}}
 ; MIPS64: daddiu  $[[T0:[0-9]+]], $zero, 1
 ; MIPS64: dsll    $[[T1:[0-9]+]], $[[T0]], 35
 ; MIPS64: and     $[[T2:[0-9]+]], $4, $[[T1]]
 ; MIPS64: bnez    $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]]
   %bit = and i64 %a, 34359738368
   %res = icmp eq i64 %bit, 0
   br i1 %res, label %endif, label %if
 if:
   ret i64 48
 
 endif:
   ret i64 12
 }
 
-define i64 @bbit1(i64 %a) nounwind {
+define i64 @bbit0(i64 %a) nounwind {
 entry:
-; ALL-LABEL: bbit1:
-; OCTEON: bbit1 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; ALL-LABEL: bbit0:
+; OCTEON: bbit0 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; OCTEON-PIC-NOT: b  {{[[:space:]].*}}
+; OCTEON-NOT: j  {{[[:space:]].*}}
 ; MIPS64: andi  $[[T0:[0-9]+]], $4, 8
 ; MIPS64: beqz  $[[T0]], [[BB0:(\$|\.L)BB[0-9_]+]]
   %bit = and i64 %a, 8
   %res = icmp ne i64 %bit, 0
   br i1 %res, label %endif, label %if
 if:
   ret i64 48
 
 endif:
   ret i64 12
 }
 
-define i64 @bbit132(i64 %a) nounwind {
+define i64 @bbit032(i64 %a) nounwind {
 entry:
-; ALL-LABEL: bbit132:
-; OCTEON: bbit132 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; ALL-LABEL: bbit032:
+; OCTEON: bbit032 $4, 3, [[BB0:(\$|\.L)BB[0-9_]+]]
+; OCTEON-PIC-NOT: b  {{[[:space:]].*}}
+; OCTEON-NOT: j  {{[[:space:]].*}}
 ; MIPS64: daddiu  $[[T0:[0-9]+]], $zero, 1
 ; MIPS64: dsll    $[[T1:[0-9]+]], $[[T0]], 35
 ; MIPS64: and     $[[T2:[0-9]+]], $4, $[[T1]]
 ; MIPS64: beqz    $[[T2]], [[BB0:(\$|\.L)BB[0-9_]+]]
   %bit = and i64 %a, 34359738368
   %res = icmp ne i64 %bit, 0
   br i1 %res, label %endif, label %if
 if:
   ret i64 48
 
 endif:
   ret i64 12
 }