[X86] Improve the unknown stepping support for Intel CPUs in getHostCPUName

[craig.topper]

Summary

This patch improves our guessing of unknown Intel CPUs to support Goldmont and skylake-avx512.

[igorb]

LGTM

[zvi]

Craig, do you plan on pushing this patch?

[craig.topper]

Yeah. I need to rebase it after by other changes to Host.cpp.

lib/Support/Host.cpp

enum ProcessorFeatures {
   FEATURE_SSE4_1,
   FEATURE_SSE4_2,
   FEATURE_AVX,
   FEATURE_AVX2,
   FEATURE_AVX512,
   FEATURE_AVX512SAVE,
   FEATURE_MOVBE,
   FEATURE_ADX,
-  FEATURE_EM64T
+  FEATURE_EM64T,
+  FEATURE_AVX512VL,
+  FEATURE_CLFLUSHOPT,
+  FEATURE_SHA,
 };
 
 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
 // support. Consequently, for i386, the presence of CPUID is checked first
 // via the corresponding eflags bit.
 // Removal of cpuid.h header motivated by PR30384
 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
case 0x5f:
       break; // "goldmont"
     case 0x57:
       *Type = INTEL_XEONPHI; // knl
       *Subtype = INTEL_KNIGHTS_LANDING;
       break;
 
     default: // Unknown family 6 CPU, try to guess.
       if (Features & (1 << FEATURE_AVX512)) {
+        if (Features & (1 << FEATURE_AVX512VL)) {
+          *Type = INTEL_COREI7;
+          *Subtype = INTEL_COREI7_SKYLAKE_AVX512;
+        } else {
           *Type = INTEL_XEONPHI; // knl
           *Subtype = INTEL_KNIGHTS_LANDING;
+        }
+        break;
+      }
+      if (Features & (1 << FEATURE_CLFLUSHOPT)) {
+        if (Features & (1 << FEATURE_SHA)) {
+          *Type = INTEL_ATOM;
+          *Subtype = INTEL_ATOM_GOLDMONT;
+        } else {
+          *Type = INTEL_COREI7;
+          *Subtype = INTEL_COREI7_SKYLAKE;
+        }
         break;
       }
       if (Features & (1 << FEATURE_ADX)) {
         *Type = INTEL_COREI7;
         *Subtype = INTEL_COREI7_BROADWELL;
         break;
       }
       if (Features & (1 << FEATURE_AVX2)) {
static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX,
   // switch, then we have full AVX support.
   const unsigned AVXBits = (1 << 27) | (1 << 28);
   bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
                 ((EAX & 0x6) == 0x6);
   bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
   bool HasLeaf7 =
       MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
   bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
+  bool HasCLFLUSHOPT = HasLeaf7 && ((EBX >> 23) & 1);
+  bool HasSHA = HasLeaf7 && ((EBX >> 29) & 1);
   bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
   bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
+  bool HasAVX512VL = HasLeaf7 && HasAVX512Save && ((EBX >> 31) & 1);
   Features |= (HasAVX << FEATURE_AVX);
   Features |= (HasAVX2 << FEATURE_AVX2);
   Features |= (HasAVX512 << FEATURE_AVX512);
   Features |= (HasAVX512Save << FEATURE_AVX512SAVE);
   Features |= (HasADX << FEATURE_ADX);
+  Features |= (HasAVX512VL << FEATURE_AVX512VL);
+  Features |= (HasCLFLUSHOPT << FEATURE_CLFLUSHOPT);
+  Features |= (HasSHA << FEATURE_SHA);
 
   getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
   Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T);
   return Features;
 }
 
 StringRef sys::getHostCPUName() {
   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;