[DAGCombiner] Fold (vextract v, (sext (trunc i))) -> (vextract v, i)

[Bigcheese]

Summary

EXTRACT_VECTOR_ELT has undefined behavior for element indices greater than
the input vector width.

[nadav]

LGTM.

[Bigcheese]

Realized that this optimization is invalid. Replaced by http://reviews.llvm.org/D3519 .

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (InOp.getValueType() != NVT) {
       return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
     }
     return InOp;
   }
 
   SDValue EltNo = N->getOperand(1);
   bool ConstEltNo = isa<ConstantSDNode>(EltNo);
 
+  // (vextract v, (sext (trunc i))) -> (vextract v, i)
+  if (EltNo.getOpcode() == ISD::SIGN_EXTEND &&
+      EltNo.getOperand(0).getOpcode() == ISD::TRUNCATE) {
+    SDValue Trunc = EltNo.getOperand(0);
+    if (Trunc.getValueType().getSizeInBits() >=
+        Log2_64_Ceil(VT.getVectorNumElements()))
+      return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), N->getValueType(0),
+                         InVec, Trunc.getOperand(0));
+  }
+
   // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
   // We only perform this optimization before the op legalization phase because
   // we may introduce new vector instructions which are not backed by TD
   // patterns. For example on AVX, extracting elements from a wide vector
   // without using extract_subvector. However, if we can find an underlying
   // scalar value, then we can always use that.
   if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
       && ConstEltNo) {

test/CodeGen/X86/vec_splat.ll

define <4 x float> @load_extract_splat(<4 x float>* nocapture readonly %ptr, i64 %i, i64 %j) nounwind {
   %5 = insertelement <4 x float> undef, float %4, i32 0
   %6 = insertelement <4 x float> %5, float %4, i32 1
   %7 = insertelement <4 x float> %6, float %4, i32 2
   %8 = insertelement <4 x float> %7, float %4, i32 3
   ret <4 x float> %8
   
 ; AVX-LABEL: load_extract_splat
 ; AVX-NOT: rsp
+; AVX-NOT: mov
 ; AVX: vbroadcastss
 }