[mips][FastISel] Correct the relocation operators for calls & data.

[sdardis]

Summary

Correct the relocation operators from %got to %call16 for function call
lowering in FastISel and correct the relocation sequences for objects which
are not visible outside their translation unit.

Data and functions which are not visible outside their translation unit are
accessed by loading the base address from the GOT and modifying that with
a %lo relocation operator.

[slthakur]

LGTM

lib/Target/Mips/MipsFastISel.cpp

if (VT != MVT::i32)
     return 0;
   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
   unsigned DestReg = createResultReg(RC);
   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
   bool IsThreadLocal = GVar && GVar->isThreadLocal();
   // TLS not supported at this time.
   if (IsThreadLocal)
     return 0;
+
+  // Materializing the address an object which _is not_ visible outside the
+  // translation unit has a sequence which is:
+  //
+  //    lw $tmp, %got($SYMBOL)($gp)
+  //    addiu $dest, $temp, %lo($SYMBOL)
+  //
+  // Data which _is_ visible outside the translation unit has a materialization
+  // sequence which is:
+  //
+  //    lw $dest, %got($SYMBOL)($gp)
+  //
+  // For functions this uses %call16 relocation operator:
+  //
+  //    lw $25, %call16($SYMBOL)($gp)
+  //
+  // Functions that are visible outside their translation unit are presumed to
+  // be subject to lazy binding, even within their defining translation unit.
+  unsigned TOF = (isa<Function>(GV) && !GV->hasInternalLinkage())
+                     ? MipsII::MO_GOT_CALL
+                     : MipsII::MO_GOT;
   emitInst(Mips::LW, DestReg)
       .addReg(MFI->getGlobalBaseReg())
-      .addGlobalAddress(GV, 0, MipsII::MO_GOT);
-  if ((GV->hasInternalLinkage() ||
-       (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
+      .addGlobalAddress(GV, 0, TOF);
+
+  if (GV->hasInternalLinkage() || GV->hasLocalLinkage()) {
+    // FIXME: Ideally, this component of the address would be folded into the
+    //        offset of the load.
     unsigned TempReg = createResultReg(RC);
     emitInst(Mips::ADDiu, TempReg)
         .addReg(DestReg)
         .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
     DestReg = TempReg;
   }
   return DestReg;
 }
 
 unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
   const TargetRegisterClass *RC = &Mips::GPR32RegClass;
   unsigned DestReg = createResultReg(RC);
   emitInst(Mips::LW, DestReg)
       .addReg(MFI->getGlobalBaseReg())
-      .addSym(Sym, MipsII::MO_GOT);
+      .addSym(Sym, MipsII::MO_GOT_CALL);
   return DestReg;
 }
 
 // Materialize a constant into a register, and return the register
 // number (or zero if we failed to handle it).
 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
   EVT CEVT = TLI.getValueType(DL, C->getType(), true);
 

test/CodeGen/Mips/Fast-ISel/callabi.ll

 }
 
 declare void @xi(i32)
 
 define void @cxi() {
   ; ALL-LABEL:    cxi:
 
   ; ALL-DAG:        addiu   $4, $zero, 10
-  ; ALL-DAG:        lw      $25, %got(xi)(${{[0-9]+}})
+  ; ALL-DAG:        lw      $25, %call16(xi)(${{[0-9]+}})
   ; ALL:            jalr    $25
   call void @xi(i32 10)
   ret void
 }
 
 declare void @xbb(i8, i8)
 
 define void @cxbb() {

 
 declare void @xii(i32, i32)
 
 define void @cxii() {
   ; ALL-LABEL:    cxii:
 
   ; ALL-DAG:        addiu   $4, $zero, 746
   ; ALL-DAG:        addiu   $5, $zero, 892
-  ; ALL-DAG:        lw      $25, %got(xii)(${{[0-9]+}})
+  ; ALL-DAG:        lw      $25, %call16(xii)(${{[0-9]+}})
   ; ALL:            jalr    $25
   call void @xii(i32 746, i32 892)
   ret void
 }
 
 declare void @xccc(i8, i8, i8)
 
 define void @cxccc() {

 declare void @xiii(i32, i32, i32)
 
 define void @cxiii() {
   ; ALL-LABEL:    cxiii:
 
   ; ALL-DAG:        addiu   $4, $zero, 88
   ; ALL-DAG:        addiu   $5, $zero, 44
   ; ALL-DAG:        addiu   $6, $zero, 11
-  ; ALL-DAG:        lw      $25, %got(xiii)(${{[0-9]+}})
+  ; ALL-DAG:        lw      $25, %call16(xiii)(${{[0-9]+}})
   ; ALL:            jalr    $25
   call void @xiii(i32 88, i32 44, i32 11)
   ret void
 }
 
 declare void @xcccc(i8, i8, i8, i8)
 
 define void @cxcccc() {

 
 define void @cxiiii() {
   ; ALL-LABEL:    cxiiii:
 
   ; ALL-DAG:        addiu   $4, $zero, 167
   ; ALL-DAG:        addiu   $5, $zero, 320
   ; ALL-DAG:        addiu   $6, $zero, 97
   ; ALL-DAG:        addiu   $7, $zero, 14
-  ; ALL-DAG:        lw      $25, %got(xiiii)(${{[0-9]+}})
+  ; ALL-DAG:        lw      $25, %call16(xiiii)(${{[0-9]+}})
   ; ALL:            jalr    $25
   call void @xiiii(i32 167, i32 320, i32 97, i32 14)
   ret void
 }
 
 @c1 = global i8 -45, align 1
 @uc1 = global i8 27, align 1
 @s1 = global i16 -1789, align 2

 
 define void @cxf() {
   ; ALL-LABEL:    cxf:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL:            lui     $[[REG_FPCONST_1:[0-9]+]], 17886
   ; ALL:            ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067
   ; ALL:            mtc1    $[[REG_FPCONST]], $f12
-  ; ALL:            lw      $25, %got(xf)($[[REG_GP]])
+  ; ALL:            lw      $25, %call16(xf)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xf(float 0x40BBC85560000000)
   ret void
 }
 
 declare void @xff(float, float)
 
 define void @cxff() {
   ; ALL-LABEL:    cxff:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 16314
   ; ALL-DAG:        ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349
   ; ALL-DAG:        mtc1    $[[REG_FPCONST]], $f12
   ; ALL-DAG:        lui     $[[REG_FPCONST_2:[0-9]+]], 16593
   ; ALL-DAG:        ori     $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642
   ; ALL-DAG:        mtc1    $[[REG_FPCONST_3]], $f14
-  ; ALL-DAG:        lw      $25, %got(xff)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xff)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000)
   ret void
 }
 
 declare void @xfi(float, i32)
 
 define void @cxfi() {
   ; ALL-LABEL:    cxfi:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 16540
   ; ALL-DAG:        ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554
   ; ALL-DAG:        mtc1    $[[REG_FPCONST]], $f12
   ; ALL-DAG:        addiu   $5, $zero, 102
-  ; ALL-DAG:        lw      $25, %got(xfi)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xfi)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xfi(float 0x4013906240000000, i32 102)
   ret void
 }
 
 declare void @xfii(float, i32, i32)
 
 define void @cxfii() {
   ; ALL-LABEL:    cxfii:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 17142
   ; ALL-DAG:        ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240
   ; ALL-DAG:        mtc1    $[[REG_FPCONST]], $f12
   ; ALL-DAG:        addiu   $5, $zero, 9993
   ; ALL-DAG:        addiu   $6, $zero, 10922
-  ; ALL-DAG:        lw      $25, %got(xfii)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xfii)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922)
   ret void
 }
 
 declare void @xfiii(float, i32, i32, i32)
 
 define void @cxfiii() {
   ; ALL-LABEL:    cxfiii:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 17120
   ; ALL-DAG:        ori     $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681
   ; ALL-DAG:        mtc1    $[[REG_FPCONST]], $f12
   ; ALL-DAG:        addiu   $5, $zero, 3948
   ; ALL-DAG:        lui     $[[REG_I_1:[0-9]+]], 1
   ; ALL-DAG:        ori     $6, $[[REG_I_1]], 23475
   ; ALL-DAG:        lui     $[[REG_I_2:[0-9]+]], 1
   ; ALL-DAG:        ori     $7, $[[REG_I_2]], 45686
-  ; ALL-DAG:        lw      $25, %got(xfiii)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xfiii)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222)
   ret void
 }
 
 declare void @xd(double)
 
 define void @cxd() {
   ; ALL-LABEL:    cxd:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 16514
   ; ALL-DAG:        ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
   ; ALL-DAG:        lui     $[[REG_FPCONST_3:[0-9]+]], 58195
   ; ALL-DAG:        ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
   ; ALL-DAG:        mtc1    $[[REG_FPCONST_4]], $f12
   ; 32R1-DAG:       mtc1    $[[REG_FPCONST_2]], $f13
   ; 32R2-DAG:       mthc1   $[[REG_FPCONST_2]], $f12
-  ; ALL-DAG:        lw      $25, %got(xd)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xd)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xd(double 5.994560e+02)
   ret void
 }
 
 declare void @xdd(double, double)
 
 define void @cxdd() {
define void @cxdd() {
   ; 32R2-DAG:       mthc1   $[[REG_FPCONST_2]], $f12
   ; ALL-DAG:        lui     $[[REG_FPCONST_1:[0-9]+]], 16629
   ; ALL-DAG:        ori     $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
   ; ALL-DAG:        lui     $[[REG_FPCONST_3:[0-9]+]], 63438
   ; ALL-DAG:        ori     $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
   ; ALL-DAG:        mtc1    $[[REG_FPCONST_4]], $f14
   ; 32R1-DAG:       mtc1    $[[REG_FPCONST_2]], $f15
   ; 32R2-DAG:       mthc1   $[[REG_FPCONST_2]], $f14
-  ; ALL-DAG:        lw      $25, %got(xdd)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xdd)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917)
   ret void
 }
 
 declare void @xif(i32, float)
 
 define void @cxif() {
   ; ALL-LABEL:    cxif:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        addiu   $4, $zero, 345
   ; ALL-DAG:        lui     $[[REGF_1:[0-9]+]], 17374
   ; ALL-DAG:        ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393
   ; ALL-DAG:        mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
   ; ALL-DAG:        mfc1    $5, $f[[REGF_3]]
-  ; ALL-DAG:        lw      $25, %got(xif)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xif)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xif(i32 345, float 0x407BCE5A20000000)
   ret void
 }
 
 declare void @xiff(i32, float, float)
 
 define void @cxiff() {
   ; ALL-LABEL:    cxiff:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        addiu   $4, $zero, 12239
   ; ALL-DAG:        lui     $[[REGF0_1:[0-9]+]], 17526
   ; ALL-DAG:        ori     $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 55706
   ; ALL-DAG:        mtc1    $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
   ; ALL-DAG:        lui     $[[REGF1_1:[0-9]+]], 16543
   ; ALL-DAG:        ori     $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 65326
   ; ALL:            mtc1    $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
   ; ALL-DAG:        mfc1    $5, $f[[REGF0_3]]
   ; ALL-DAG:        mfc1    $6, $f[[REGF1_3]]
-  ; ALL-DAG:        lw      $25, %got(xiff)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xiff)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000)
   ret void
 }
 
 declare void @xifi(i32, float, i32)
 
 define void @cxifi() {
   ; ALL-LABEL:    cxifi:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        addiu   $4, $zero, 887
   ; ALL-DAG:        lui     $[[REGF_1:[0-9]+]], 16659
   ; ALL-DAG:        ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759
   ; ALL-DAG:        mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
   ; ALL-DAG:        mfc1    $5, $f[[REGF_3]]
   ; ALL-DAG:        addiu   $6, $zero, 888
-  ; ALL-DAG:        lw      $25, %got(xifi)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xifi)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xifi(i32 887, float 0x402277CEE0000000, i32 888)
   ret void
 }
 
 declare void @xifif(i32, float, i32, float)
 
 define void @cxifif() {
   ; ALL-LABEL:    cxifif:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        lui     $[[REGI:[0-9]+]], 1
   ; ALL-DAG:        ori     $4, $[[REGI]], 2238
   ; ALL-DAG:        lui     $[[REGF0_1:[0-9]+]], 17527
   ; ALL-DAG:        ori     $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 2015
   ; ALL-DAG:        mtc1    $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
   ; ALL-DAG:        addiu   $6, $zero, 9991
   ; ALL-DAG:        lui     $[[REGF1_1:[0-9]+]], 17802
   ; ALL-DAG:        ori     $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 58470
   ; ALL:            mtc1    $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
   ; ALL-DAG:        mfc1    $5, $f[[REGF0_3]]
   ; ALL-DAG:        mfc1    $7, $f[[REGF1_3]]
-  ; ALL-DAG:        lw      $25, %got(xifif)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xifif)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xifif(i32 67774, float 0x408EE0FBE0000000,
                    i32 9991, float 0x40B15C8CC0000000)
   ret void
 }
 
 declare void @xiffi(i32, float, float, i32)
 
 define void @cxiffi() {
   ; ALL-LABEL:    cxiffi:
 
   ; ALL:            addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:        addiu   $4, $zero, 45
   ; ALL-DAG:        lui     $[[REGF0_1:[0-9]+]], 16307
   ; ALL-DAG:        ori     $[[REGF0_2:[0-9]+]], $[[REGF0_1]], 13107
   ; ALL-DAG:        mtc1    $[[REGF0_2]], $f[[REGF0_3:[0-9]+]]
   ; ALL-DAG:        lui     $[[REGF1_1:[0-9]+]], 17529
   ; ALL-DAG:        ori     $[[REGF1_2:[0-9]+]], $[[REGF1_1]], 39322
   ; ALL:            mtc1    $[[REGF1_2]], $f[[REGF1_3:[0-9]+]]
   ; ALL-DAG:        addiu   $7, $zero, 234
   ; ALL-DAG:        mfc1    $5, $f[[REGF0_3]]
   ; ALL-DAG:        mfc1    $6, $f[[REGF1_3]]
-  ; ALL-DAG:        lw      $25, %got(xiffi)($[[REG_GP]])
+  ; ALL-DAG:        lw      $25, %call16(xiffi)($[[REG_GP]])
   ; ALL:            jalr    $25
   call void @xiffi(i32 45, float 0x3FF6666660000000,
                    float 0x408F333340000000, i32 234)
   ret void
 }
 
 declare void @xifii(i32, float, i32, i32)
 
 define void @cxifii() {
   ; ALL-LABEL:    cxifii:
 
   ; ALL-DAG:    addu    $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
   ; ALL-DAG:    addiu   $4, $zero, 12239
   ; ALL-DAG:    lui     $[[REGF_1:[0-9]+]], 17526
   ; ALL-DAG:    ori     $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
   ; ALL-DAG:    mtc1    $[[REGF_2]], $f[[REGF_3:[0-9]+]]
   ; ALL-DAG:    mfc1    $5, $f[[REGF_3]]
   ; ALL-DAG:    lui     $[[REGI2:[0-9]+]], 15
   ; ALL-DAG:    ori     $6, $[[REGI2]], 15837
   ; ALL-DAG:    addiu   $7, $zero, 1234
-  ; ALL-DAG:    lw      $25, %got(xifii)($[[REG_GP]])
+  ; ALL-DAG:    lw      $25, %call16(xifii)($[[REG_GP]])
   ; ALL:        jalr    $25
   call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234)
   ret void
 }
+
+define internal void @call_cxifii() {
+  ; ALL-LABEL: call_cxifii:
+  ; ALL: lw     $[[R0:[0-9]+]], %call16(cxifii)(${{[0-9gp]+}})
+  ; ALL: jalr   $[[R0]]
+  call void @cxifii()
+  ret void
+}
+
+define void @call_call_cxifii() {
+  ; ALL-LABEL: call_call_cxifii:
+  ; ALL: lw $[[R0:[0-9]+]], %got(call_cxifii)(${{[0-9gp]+}})
+  ; ALL: addiu $[[R1:[0-9]+]], $[[R0]], %lo(call_cxifii)
+  ; ALL: jalr $[[R1]]
+  call void @call_cxifii()
+  ret void
+}
+
+@ab = global i32 1, align 4
+@ab2 = internal global i32 2, align 4
+
+declare i32 @ciii(i32)
+
+define i32 @call_ciii() {
+entry:
+  ; ALL-LABEL: call_ciii:
+  ; ALL: lw    $[[R0:[0-9]+]], %got(ab)(${{[0-9]+}})
+  ; ALL: lw    ${{[0-9]+}}, 0($[[R0]])
+  ; ALL: lw    $25, %call16(ciii)(${{[0-9]+}})
+  ; ALL: jalr  $25
+  ; ALL: lw    $[[R1:[0-9]+]], %got(ab2)(${{[0-9]+}})
+  ; ALL: addiu $[[R2:[0-9]+]], $[[R1]], %lo(ab2)
+  ; ALL: lw   ${{[0-9]+}}, 0($[[R2]])
+  ; ALL: lw    $25, %call16(ciii)(${{[0-9]+}})
+  ; ALL: jalr  $25
+  %0 = load i32, i32 * @ab
+  %1 = call i32 @ciii(i32 %0)
+  %2 = load i32, i32 * @ab2
+  %3 = call i32 @ciii(i32 %2)
+  %4 = add i32 %3, %1
+  ret i32 %4
+}

test/CodeGen/Mips/Fast-ISel/memtest1.ll

define void @cpy(i8* %src, i32 %i) {
 
   ; ALL-DAG:        lw    $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
   ; ALL-DAG:        sw    $4, 24($sp)
   ; ALL-DAG:        move  $4, $[[T0]]
   ; ALL-DAG:        sw    $5, 20($sp)
   ; ALL-DAG:        lw    $[[T1:[0-9]+]], 24($sp)
   ; ALL-DAG:        move  $5, $[[T1]]
   ; ALL-DAG:        lw    $6, 20($sp)
-  ; ALL-DAG:        lw    $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}})
+  ; ALL-DAG:        lw    $[[T2:[0-9]+]], %call16(memcpy)(${{[0-9]+}})
   ; ALL:            jalr  $[[T2]]
   ; ALL-NEXT:       nop
   ; ALL-NOT:        {{.*}}$2{{.*}}
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0),
                                        i8* %src, i32 %i, i32 1, i1 false)
   ret void
 }
 
 define void @mov(i8* %src, i32 %i) {
   ; ALL-LABEL:  mov:
 
 
   ; ALL-DAG:        lw    $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
   ; ALL-DAG:        sw    $4, 24($sp)
   ; ALL-DAG:        move  $4, $[[T0]]
   ; ALL-DAG:        sw    $5, 20($sp)
   ; ALL-DAG:        lw    $[[T1:[0-9]+]], 24($sp)
   ; ALL-DAG:        move  $5, $[[T1]]
   ; ALL-DAG:        lw    $6, 20($sp)
-  ; ALL-DAG:        lw    $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}})
+  ; ALL-DAG:        lw    $[[T2:[0-9]+]], %call16(memmove)(${{[0-9]+}})
   ; ALL:            jalr  $[[T2]]
   ; ALL-NEXT:       nop
   ; ALL-NOT:        {{.*}}$2{{.*}}
   call void @llvm.memmove.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0),
                                         i8* %src, i32 %i, i32 1, i1 false)
   ret void
 }
 
 define void @clear(i32 %i) {
   ; ALL-LABEL:  clear:
 
   ; ALL-DAG:        lw    $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
   ; ALL-DAG:        sw    $4, 16($sp)
   ; ALL-DAG:        move  $4, $[[T0]]
   ; ALL-DAG:        addiu $[[T1:[0-9]+]], $zero, 42
   ; 32R1-DAG:       sll   $[[T2:[0-9]+]], $[[T1]], 24
   ; 32R1-DAG:       sra   $5, $[[T2]], 24
   ; 32R2-DAG:       seb   $5, $[[T1]]
   ; ALL-DAG:        lw    $6, 16($sp)
-  ; ALL-DAG:        lw    $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}})
+  ; ALL-DAG:        lw    $[[T2:[0-9]+]], %call16(memset)(${{[0-9]+}})
   ; ALL:            jalr  $[[T2]]
   ; ALL-NEXT:       nop
   ; ALL-NOT:        {{.*}}$2{{.*}}
   call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0),
                                   i8 42, i32 %i, i32 1, i1 false)
   ret void
 }