Add Simple return instruction to Mips fast-isel

[rkotler]

Summary

Add code to do the simple return instruction

[dsanders]

Did you mean to update D3404 rather than create a new patch? It looks like it's the same change with the test case added and EnableMipsFastISel defaulted to true.

[dsanders]

LGTM with a couple whitespace nits. There's also a query as to whether the change to enable -mips-fast-isel by default was intentional.

This is an update D3404 that was accidentally submitted as a new patch. I'll close D3430

lib/Target/Mips/MipsISelLowering.cpp

56

As discussed, I'm in favour of it being enabled by default but I ought to ask if it was intentional.

test/CodeGen/Mips/Fast-ISel/nullvoid.ll

1–2

There's trailing whitespace on the second RUN line.
Could you also add a couple spaces before the '<'? It gives another clue that it's a continued line.

10–11

Blank lines at EOF

[rkotler]

I had changed init to true because management instructed me to do so.

But I've been arguing for it to be false.

But it seems everyone else wants it to be true.

I will enable it to be true but submit that as a separate one line patch.

[dsanders]

It seems I forgot to mark this patch accepted. Done

[rkotler]

• fix test case so that it only works if all fast-isel patterns are matched. also add one line omitted from select ret that is needed in all other ports for fast-isel

[rkotler]

Clean up git error

[rkotler]

• get rid of uneeded file

[rkotler]

-O0 was need for the test case in order to enable -fast-isel. It would also have been possible to just add -fast-isel.
-fast-isel-abort requires that -fast-isel is already enabled.

[dsanders]

The new version LGTM

[rkotler]

Make -fast-isel off for now by default for Mips

[dsanders]

New version LGTM

[rkotler]

need mips-fast-isel to enable test - fix test case

[rkotler]

Closed by commit rL207565 (authored by @rkotler).

lib/Target/Mips/MipsFastISel.cpp

 //===-- MipsastISel.cpp - Mips FastISel implementation
 //---------------------===//
 
 #include "llvm/CodeGen/FunctionLoweringInfo.h"
 #include "llvm/CodeGen/FastISel.h"
+
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetLibraryInfo.h"
 #include "MipsISelLowering.h"
+#include "MipsMachineFunction.h"
+#include "MipsSubtarget.h"
 
 using namespace llvm;
 
 namespace {
 
 class MipsFastISel final : public FastISel {
 
+  /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
+  /// make the right decision when generating code for different targets.
+  const MipsSubtarget *Subtarget;
+  Module &M;
+  const TargetMachine &TM;
+  const TargetInstrInfo &TII;
+  const TargetLowering &TLI;
+  MipsFunctionInfo *MFI;
+
+  // Convenience variables to avoid some queries.
+  LLVMContext *Context;
+
+  bool TargetSupported;
+
 public:
   explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
                         const TargetLibraryInfo *libInfo)
-      : FastISel(funcInfo, libInfo) {}
-  bool TargetSelectInstruction(const Instruction *I) override { return false; }
+      : FastISel(funcInfo, libInfo),
+        M(const_cast<Module &>(*funcInfo.Fn->getParent())),
+        TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()),
+        TLI(*TM.getTargetLowering()) {
+    Subtarget = &TM.getSubtarget<MipsSubtarget>();
+    MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
+    Context = &funcInfo.Fn->getContext();
+    TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
+                       (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));
+  }
+
+  bool TargetSelectInstruction(const Instruction *I) override;
+
+  bool SelectRet(const Instruction *I);
 };
+
+bool MipsFastISel::SelectRet(const Instruction *I) {
+  const ReturnInst *Ret = cast<ReturnInst>(I);
+  if (Ret->getNumOperands() > 0) {
+    return false;
+  }
+  unsigned RetOpc = Mips::RetRA;
+  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(RetOpc));
+  return true;
+}
+
+bool MipsFastISel::TargetSelectInstruction(const Instruction *I) {
+  if (!TargetSupported)
+    return false;
+  switch (I->getOpcode()) {
+  default:
+    break;
+  case Instruction::Ret:
+    return SelectRet(I);
+  }
+  return false;
+}
 }
 
 namespace llvm {
 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
                                const TargetLibraryInfo *libInfo) {
   return new MipsFastISel(funcInfo, libInfo);
 }
 }

lib/Target/Mips/MipsISelLowering.cpp

 static cl::opt<bool>
 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
                cl::desc("MIPS: Don't trap on integer division by zero."),
                cl::init(false));
 
 cl::opt<bool>
 EnableMipsFastISel("mips-fast-isel", cl::Hidden,
   cl::desc("Allow mips-fast-isel to be used"),
-  cl::init(false));
+  cl::init(true));
 
 static const MCPhysReg O32IntRegs[4] = {
   Mips::A0, Mips::A1, Mips::A2, Mips::A3
 };
 
 static const MCPhysReg Mips64IntRegs[8] = {
   Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
   Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64

test/CodeGen/Mips/Fast-ISel/nullvoid.ll

+; RUN: llc -march=mipsel -relocation-model=pic -fast-isel -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s 
+
+; Function Attrs: nounwind
+define void @foo() {
+entry:
+  ret void
+; CHECK: jr $ra
+}
+
+