[mips][microMIPS] Extending size reduction pass with XOR16

[milena.vujosevic.janicic]

Summary

The patch extends size reduction pass for MicroMIPS.
XOR instruction is transformed into 16-bit instruction XOR16, if possible.

[sdardis]

LGTM with inline comments addressed.

lib/Target/Mips/MicroMipsSizeReduction.cpp

460–475 ↗

(On Diff #102669)

Change this if..else chain to switch on OpTransfer, with a default case of llvm_unreachable.

496 ↗

(On Diff #102669)

There's a small 'gotcha' here, if Subtarget->hasMips64r6() is true, Subtarget->hasMips32r6() is also true. So "|| Subtarget->hasMips64r6()" can be removed.

hasMips64(rX)() implies hasMips32(rX)() is also true, due to the way the architecture is defined, so generally you only need to check for the availability of the 32bit revision of the ISA to determine what revision is being targeted.

llvm/trunk/lib/Target/Mips/MicroMipsSizeReduction.cpp

 
 /// Order of operands to transfer
 // TODO: Will be extended when additional optimizations are added
 enum OperandTransfer {
   OT_NA,          ///< Not applicable
   OT_OperandsAll, ///< Transfer all operands
   OT_Operands02,  ///< Transfer operands 0 and 2
   OT_Operand2,    ///< Transfer just operand 2
+  OT_OperandsXOR, ///< Transfer operands for XOR16
 };
 
 /// Reduction type
 // TODO: Will be extended when additional optimizations are added
 enum ReduceType {
   RT_OneInstr ///< Reduce one instruction into a smaller instruction
 };
 
private:
   // returns true on success.
   static bool ReduceADDIUToADDIUSP(MachineInstr *MI, const ReduceEntry &Entry);
 
   // Attempts to reduce ADDIU into ADDIUR1SP instruction,
   // returns true on success.
   static bool ReduceADDIUToADDIUR1SP(MachineInstr *MI,
                                      const ReduceEntry &Entry);
 
+  // Attempts to reduce XOR into XOR16 instruction,
+  // returns true on success.
+  static bool ReduceXORtoXOR16(MachineInstr *MI, const ReduceEntry &Entry);
+
   // Changes opcode of an instruction.
   static bool ReplaceInstruction(MachineInstr *MI, const ReduceEntry &Entry);
 
   // Table with transformation rules for each instruction.
   static llvm::SmallVector<ReduceEntry, 16> ReduceTable;
 };
 
 char MicroMipsSizeReduce::ID = 0;
llvm::SmallVector<ReduceEntry, 16> MicroMipsSizeReduce::ReduceTable = {
      ImmField(0, 0, 0, -1)},
     {RT_OneInstr, OpCodes(Mips::SUBu_MM, Mips::SUBU16_MM),
      ReduceArithmeticInstructions, OpInfo(OT_OperandsAll),
      ImmField(0, 0, 0, -1)},
     {RT_OneInstr, OpCodes(Mips::SW, Mips::SWSP_MM), ReduceXWtoXWSP,
      OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
     {RT_OneInstr, OpCodes(Mips::SW_MM, Mips::SWSP_MM), ReduceXWtoXWSP,
      OpInfo(OT_OperandsAll), ImmField(2, 0, 32, 2)},
-};
+    {RT_OneInstr, OpCodes(Mips::XOR, Mips::XOR16_MM), ReduceXORtoXOR16,
+     OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)},
+    {RT_OneInstr, OpCodes(Mips::XOR_MM, Mips::XOR16_MM), ReduceXORtoXOR16,
+     OpInfo(OT_OperandsXOR), ImmField(0, 0, 0, -1)}};
 } // namespace
 
 // Returns true if the machine operand MO is register SP.
 static bool IsSP(const MachineOperand &MO) {
   if (MO.isReg() && ((MO.getReg() == Mips::SP)))
     return true;
   return false;
 }
bool MicroMipsSizeReduce::ReduceSXtoSX16(MachineInstr *MI,
 
   if (!isMMSourceRegister(MI->getOperand(0)) ||
       !isMMThreeBitGPRegister(MI->getOperand(1)))
     return false;
 
   return ReplaceInstruction(MI, Entry);
 }
 
+bool MicroMipsSizeReduce::ReduceXORtoXOR16(MachineInstr *MI,
+                                           const ReduceEntry &Entry) {
+  if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
+      !isMMThreeBitGPRegister(MI->getOperand(1)) ||
+      !isMMThreeBitGPRegister(MI->getOperand(2)))
+    return false;
+
+  if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
+      !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
+    return false;
+
+  return ReplaceInstruction(MI, Entry);
+}
+
 bool MicroMipsSizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
   bool Modified = false;
   MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
                                     E = MBB.instr_end();
   MachineBasicBlock::instr_iterator NextMII;
 
   // Iterate through the instructions in the basic block
   for (; MII != E; MII = NextMII) {
if (OpTransfer == OT_OperandsAll) {
     MI->setDesc(MipsII->get(Entry.NarrowOpc()));
     DEBUG(dbgs() << "       to 16-bit: " << *MI);
     return true;
   } else {
     MachineBasicBlock &MBB = *MI->getParent();
     const MCInstrDesc &NewMCID = MipsII->get(Entry.NarrowOpc());
     DebugLoc dl = MI->getDebugLoc();
     MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
-
-    if (OpTransfer == OT_Operand2)
+    switch (OpTransfer) {
+    case OT_Operand2:
+      MIB.add(MI->getOperand(2));
+      break;
+    case OT_Operands02: {
+      MIB.add(MI->getOperand(0));
+      MIB.add(MI->getOperand(2));
+      break;
+    }
+    case OT_OperandsXOR: {
+      if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {
+        MIB.add(MI->getOperand(0));
+        MIB.add(MI->getOperand(1));
         MIB.add(MI->getOperand(2));
-    else if (OpTransfer == OT_Operands02) {
+      } else {
         MIB.add(MI->getOperand(0));
         MIB.add(MI->getOperand(2));
-    } else
+        MIB.add(MI->getOperand(1));
+      }
+      break;
+    }
+    default:
       llvm_unreachable("Unknown operand transfer!");
+    }
 
     // Transfer MI flags.
     MIB.setMIFlags(MI->getFlags());
 
     DEBUG(dbgs() << "       to 16-bit: " << *MIB);
     MBB.erase_instr(MI);
     return true;
   }

llvm/trunk/test/CodeGen/Mips/micromips-sizereduction/micromips-xor16.ll

+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -verify-machineinstrs < %s | FileCheck %s
+
+; Function Attrs: nounwind readnone
+define i1 @fun(i32 %a, i32 %b) {
+entry:
+; CHECK-LABEL: fun:
+; CHECK: xor16
+  %reg1 = or i32 %a, %b
+  %reg2 = xor i32 %reg1, -1
+  %bool1 = icmp ne i32 %a, -1
+  %bool1.ext = zext i1 %bool1 to i32
+  %bool2 = icmp eq i32 %bool1.ext, %reg2
+  ret i1 %bool2
+}