[PowerPC] fix potential verification errors on CFENCE8

[inouehrs]

Summary

This patch fixes a potential verification error (64-bit register operands for cmpw) with -verify-machineinstrs while expanding CFENCE8 into cmp + bc + isync.
As far as I read the references, we can use cmpd (or any compare instruction) for this purpose.
http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html

[inouehrs]

• added patch for test cases, which I forgot to include in the first version

[timshen]

cmpd should work as well. Both cmpw and cmpd are mnemonics of the instruction cmp, so I don't expect a performance difference.

llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp

if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
       Opcode = LowerOpcode;
     else
       Opcode = UpperOpcode;
     MI.setDesc(get(Opcode));
     return true;
   }
   case PPC::CFENCE8: {
     auto Val = MI.getOperand(0).getReg();
-    BuildMI(MBB, MI, DL, get(PPC::CMPW), PPC::CR7).addReg(Val).addReg(Val);
+    BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
     BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
         .addImm(PPC::PRED_NE_MINUS)
         .addReg(PPC::CR7)
         .addImm(1);
     MI.setDesc(get(PPC::ISYNC));
     MI.RemoveOperand(0);
     return true;
   }

llvm/trunk/test/CodeGen/PowerPC/atomic-2.ll

 }
 
 define i64 @atomic_load(i64* %mem) nounwind {
 entry:
 ; CHECK: @atomic_load
   %tmp = load atomic i64, i64* %mem acquire, align 64
 ; CHECK-NOT: ldarx
 ; CHECK: ld [[VAL:r[0-9]+]]
-; CHECK: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
+; CHECK: cmpd [[CR:cr[0-9]+]], [[VAL]], [[VAL]]
 ; CHECK: bne- [[CR]], .+4
 ; CHECK: isync
   ret i64 %tmp
 }
 

llvm/trunk/test/CodeGen/PowerPC/atomics-constant.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s | FileCheck %s
 
 target triple = "powerpc64le-unknown-linux-gnu"
 
 @a = constant i64 zeroinitializer
 
 define i64 @foo() {
 ; CHECK-LABEL: foo:
 ; CHECK:       # BB#0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LC0@toc@ha
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    ld 3, .LC0@toc@l(3)
-; CHECK-NEXT:    cmpw 7, 4, 4
+; CHECK-NEXT:    cmpd 7, 4, 4
 ; CHECK-NEXT:    ld 3, 0(3)
 ; CHECK-NEXT:    bne- 7, .+4
 ; CHECK-NEXT:    isync
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
 entry:
   %value = load atomic i64, i64* @a acquire, align 8
   ret i64 %value
 }

llvm/trunk/test/CodeGen/PowerPC/atomics-regression.ll

; PPC64LE-NEXT:    blr
   %val = load atomic i8, i8* %ptr monotonic, align 1
   ret i8 %val
 }
 
 define i8 @test2(i8* %ptr) {
 ; PPC64LE-LABEL: test2:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    lbz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
   %val = load atomic i8, i8* %ptr acquire, align 1
   ret i8 %val
 }
 
 define i8 @test3(i8* %ptr) {
 ; PPC64LE-LABEL: test3:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    lbz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
   %val = load atomic i8, i8* %ptr seq_cst, align 1
   ret i8 %val
 }
 
 define i16 @test4(i16* %ptr) {
; PPC64LE-NEXT:    blr
   %val = load atomic i16, i16* %ptr monotonic, align 2
   ret i16 %val
 }
 
 define i16 @test6(i16* %ptr) {
 ; PPC64LE-LABEL: test6:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    lhz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
   %val = load atomic i16, i16* %ptr acquire, align 2
   ret i16 %val
 }
 
 define i16 @test7(i16* %ptr) {
 ; PPC64LE-LABEL: test7:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    lhz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
   %val = load atomic i16, i16* %ptr seq_cst, align 2
   ret i16 %val
 }
 
 define i32 @test8(i32* %ptr) {
; PPC64LE-NEXT:    blr
   %val = load atomic i32, i32* %ptr monotonic, align 4
   ret i32 %val
 }
 
 define i32 @test10(i32* %ptr) {
 ; PPC64LE-LABEL: test10:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    lwz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
   %val = load atomic i32, i32* %ptr acquire, align 4
   ret i32 %val
 }
 
 define i32 @test11(i32* %ptr) {
 ; PPC64LE-LABEL: test11:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    lwz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
   %val = load atomic i32, i32* %ptr seq_cst, align 4
   ret i32 %val
 }
 
 define i64 @test12(i64* %ptr) {
; PPC64LE-NEXT:    blr
   %val = load atomic i64, i64* %ptr monotonic, align 8
   ret i64 %val
 }
 
 define i64 @test14(i64* %ptr) {
 ; PPC64LE-LABEL: test14:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    ld 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
   %val = load atomic i64, i64* %ptr acquire, align 8
   ret i64 %val
 }
 
 define i64 @test15(i64* %ptr) {
 ; PPC64LE-LABEL: test15:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:    ori 2, 2, 0
 ; PPC64LE-NEXT:    ld 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    blr
   %val = load atomic i64, i64* %ptr seq_cst, align 8
   ret i64 %val
 }
 
 define void @test16(i8* %ptr, i8 %val) {
; PPC64LE-NEXT:    blr
   ret i64 %ret
 }
 
 ; The second load should never be scheduled before isync.
 define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) {
 ; PPC64LE-LABEL: test_ordering0:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    lwz 4, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 4, 4
+; PPC64LE-NEXT:    cmpd 7, 4, 4
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    lwz 3, 0(3)
 ; PPC64LE-NEXT:    add 3, 4, 3
 ; PPC64LE-NEXT:    blr
   %val1 = load atomic i32, i32* %ptr1 acquire, align 4
   %val2 = load i32, i32* %ptr1
   %add = add i32 %val1, %val2
   ret i32 %add
 }
 
 ; The second store should never be scheduled before isync.
 define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) {
 ; PPC64LE-LABEL: test_ordering1:
 ; PPC64LE:       # BB#0:
 ; PPC64LE-NEXT:    lwz 3, 0(3)
-; PPC64LE-NEXT:    cmpw 7, 3, 3
+; PPC64LE-NEXT:    cmpd 7, 3, 3
 ; PPC64LE-NEXT:    bne- 7, .+4
 ; PPC64LE-NEXT:    isync
 ; PPC64LE-NEXT:    stw 4, 0(5)
 ; PPC64LE-NEXT:    blr
   %val2 = load atomic i32, i32* %ptr1 acquire, align 4
   store i32 %val1, i32* %ptr2
   ret i32 %val2
 }