MipsAsmParser: Fix a couple of memory leaks

[chapuni]

Summary

1. Manage Mem.Base.
2. Be responsible to release temporary Operands in MipsAsmParser::ParseRegister().

See also; http://lab.llvm.org:8011/builders/llvm-x86_64-linux-vg_leak
Feel free to rewrite and commit one as yourselves.

[dsanders]

LGTM. Thanks for looking into this.

[chapuni]

Applied in r206292 and r206293, thanks!

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

bool isMSACtrlAsmReg() const {
     return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
   }
 
   /// getStartLoc - Get the location of the first token of this operand.
   SMLoc getStartLoc() const { return StartLoc; }
   /// getEndLoc - Get the location of the last token of this operand.
   SMLoc getEndLoc() const { return EndLoc; }
 
+  virtual ~MipsOperand() {
+    switch (Kind) {
+    case k_Immediate:
+      break;
+    case k_Memory:
+      delete Mem.Base;
+      break;
+    case k_PhysRegister:
+    case k_RegisterIndex:
+    case k_Token:
+      break;
+    }
+  }
+
   virtual void print(raw_ostream &OS) const {
     switch (Kind) {
     case k_Immediate:
       OS << "Imm<";
       Imm.Val->print(OS);
       OS << ">";
       break;
     case k_Memory:
if (ResTy == MatchOperand_Success) {
     // directives.
     // Don't worry about eating tokens before failing. Using an unrecognised
     // register is a parse error.
     if (Operand.isGPRAsmReg()) {
       // Resolve to GPR32 or GPR64 appropriately.
       RegNo = isGP64() ? Operand.getGPR64Reg() : Operand.getGPR32Reg();
     }
 
+    delete &Operand;
+
     return (RegNo == (unsigned)-1);
   }
 
   assert(Operands.size() == 0);
   return (RegNo == (unsigned)-1);
 }
 
 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {