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[InstSimplify] Simplify uadd/sadd/umul/smul with overflow intrinsics when the Zero or Undef is on the LHS.
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Authored by craig.topper on May 23 2017, 4:27 PM.

Details

Summary

This code was migrated from InstCombine a few years ago. InstCombine had nearby code that would move Constants to the RHS for these, but InstSimplify doesn't have such code on this path.

Diff Detail

Repository
rL LLVM

Event Timeline

craig.topper created this revision.May 23 2017, 4:27 PM
spatel accepted this revision.May 24 2017, 8:25 AM

LGTM.

I acknowledge that there are concerns about division-of-labor between InstSimplify and InstCombine as well as the combination of those two with other passes (see current llvm-dev threads about compile-time), but handling commuted variants of existing patterns is always good (makes the pass behavior more consistent) and cheap (if it's not, then that's an independent problem).

This revision is now accepted and ready to land.May 24 2017, 8:25 AM
This revision was automatically updated to reflect the committed changes.