[X86][AVX-512] Allow EVEX encoded instruction selection when available for mul v8i32.

[igorb]

Summary

Allow EVEX encoded instruction selection when available for mul v8i32.

[craig.topper]

lib/Target/X86/X86InstrSSE.td

6725

This looks like a change for VPCMPEQQ to remove NoVLX.

[igorb]

lib/Target/X86/X86InstrSSE.td

6725

AVX512 version of vpcmpeqq is not equivalent to AVX one. I think it was disabled by mistake.

AVX
Src: (X86pcmpeq:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)
Dst: (VPCMPEQQrr:v2i64 VR128:v2i64:$src1, VR128:v2i64:$src2)

AVX512
Src: (X86pcmpeqm:v2i1 VR128X:v2i64:$src1, VR128X:v2i64:$src2)
Dst: (VPCMPEQQZ128rr:v2i1 VR128X:v2i64:$src1, VR128X:v2i64:$src2)

[craig.topper]

I'm sure it was a mistake, but I think it should be split from this patch and done as a pre-commit.

test/CodeGen/X86/avx-isa-check.ll

683

What is this test really testing? Just that isel doesn't fail if you do a v8i32 mul with various isel combinations? It doesn't look like it tests which instruction is emitted. Would this test case even fail if you put it in with no other changes? If that's correct I think we should have a test that checks which instruction is emitted.

[igorb]

• Add test, base on encoding.

[igorb]

I think we can base the predicate checks on encoding and "EVEX TO VEX Compression". I will pre-commit changes to avx512vl-arith.ll if the approach is acceptable.
In GlobalIsel https://reviews.llvm.org/D32698 i explicit check every instruction selection.

test/CodeGen/X86/avx-isa-check.ll

683

yes, It only check that isel doesn't fail with various isel combinations.

[craig.topper]

LGTM

lib/Target/X86/X86InstrSSE.td

defm PMULDQ   : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
                                   VR128, memopv2i64, i128mem,
                                   SSE_INTMUL_ITINS_P, 1>;
 }
 
 let Predicates = [HasAVX, NoVLX] in
   defm VPMULLD  : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
                                  loadv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
                                  VEX_4V, VEX_WIG;
 let Predicates = [HasAVX] in
   defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
                                  loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
                                  VEX_4V, VEX_WIG;
 
-let Predicates = [HasAVX2] in {
+let Predicates = [HasAVX2, NoVLX] in
   defm VPMULLDY  : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
                                   loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
                                   VEX_4V, VEX_L, VEX_WIG;
+let Predicates = [HasAVX2] in
   defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
                                   loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
                                   VEX_4V, VEX_L, VEX_WIG;
-}
 
 let Constraints = "$src1 = $dst" in {
   defm PMULLD  : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
                                 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
   defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
                                 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
 }
 

test/CodeGen/X86/avx-isa-check.ll

define   <8 x float> @_inreg8xfloat(float %a) {
   ret <8 x float> %c
 }
 
 define   <4 x double> @_inreg4xdouble(double %a) {
   %b = insertelement <4 x double> undef, double %a, i32 0
   %c = shufflevector <4 x double> %b, <4 x double> undef, <4 x i32> zeroinitializer
   ret <4 x double> %c
 }
+
+define <8 x i32> @test_mul_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) #0 {
+  %ret = mul <8 x i32> %arg1, %arg2
+  ret <8 x i32> %ret
+}

test/CodeGen/X86/avx512vl-arith.ll

 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %x = sub <8 x i32> %i, %j
   ret <8 x i32> %x
 }
 
 define <8 x i32> @vpmulld256_test(<8 x i32> %i, <8 x i32> %j) {
 ; CHECK-LABEL: vpmulld256_test:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    vpmulld %ymm1, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x40,0xc1]
+; CHECK-NEXT:    vpmulld %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x40,0xc1]
 ; CHECK-NEXT:    retq ## encoding: [0xc3]
   %x = mul <8 x i32> %i, %j
   ret <8 x i32> %x
 }
 
 define <4 x double> @test_vaddpd_256(<4 x double> %y, <4 x double> %x) {
 ; CHECK-LABEL: test_vaddpd_256:
 ; CHECK:       ## BB#0: ## %entry