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Differential D32286

[mips] Fix test mips64fpldst.ll with machine verifier enabled
ClosedPublic

Authored by slthakur on Apr 20 2017, 4:54 AM.

Details

Reviewers
sdardis
Summary

Removed micro mips register classes for gp initialization because gp initialization uses pure mips64 instruction. Even when compiling for micro mips, gp initialization can be done with pure mips64 instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

slthakur created this revision.Apr 20 2017, 4:54 AM
Herald added a subscriber: arichardson. · View Herald TranscriptApr 20 2017, 4:54 AM
sdardis accepted this revision.Apr 21 2017, 6:22 AM

LGTM.

This revision is now accepted and ready to land.Apr 21 2017, 6:22 AM
slthakur mentioned this in rL301394: [mips] Fix test mips64fpldst.ll with machine verifier enabled.Apr 26 2017, 4:53 AM
slthakur closed this revision.Apr 26 2017, 4:53 AM

Committed in revision 301394

Revision Contents

PathSize
lib/
Target/
Mips/
6 lines
test/
CodeGen/
Mips/
llvm-ir/
2 lines
12 lines
11 lines
11 lines
6 lines
2 lines
12 lines
tailcall/
4 lines

Diff 95933

lib/Target/Mips/MipsMachineFunction.cpp

Show All 34 Lines if (GlobalBaseReg)
return GlobalBaseReg; return GlobalBaseReg;
MipsSubtarget const &STI = MipsSubtarget const &STI =
static_cast<const MipsSubtarget &>(MF.getSubtarget()); static_cast<const MipsSubtarget &>(MF.getSubtarget());
const TargetRegisterClass *RC = const TargetRegisterClass *RC =
STI.inMips16Mode() STI.inMips16Mode()
? &Mips::CPU16RegsRegClass ? &Mips::CPU16RegsRegClass
: STI.inMicroMipsMode()
? STI.hasMips64()
? &Mips::GPRMM16_64RegClass
: &Mips::GPRMM16RegClass
: static_cast<const MipsTargetMachine &>(MF.getTarget()) : static_cast<const MipsTargetMachine &>(MF.getTarget())
.getABI() .getABI()
.IsN64() .IsN64()
? &Mips::GPR64RegClass ? &Mips::GPR64RegClass
: &Mips::GPR32RegClass; : &Mips::GPR32RegClass;
return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
} }
void MipsFunctionInfo::createEhDataRegsFI() { void MipsFunctionInfo::createEhDataRegsFI() {
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

test/CodeGen/Mips/llvm-ir/mul.ll

Show First 20 Lines • Show All 262 Lines • ▼ Show 20 Lines; ALL-LABEL: mul_i128:
; MM64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6 ; MM64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6
; MM64R6: dmuhu $[[T2:[0-9]+]], $5, $7 ; MM64R6: dmuhu $[[T2:[0-9]+]], $5, $7
; MM64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] ; MM64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
; MM64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7 ; MM64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7
; MM64R6: daddu $2, $[[T1]], $[[T0]] ; MM64R6: daddu $2, $[[T1]], $[[T0]]
; MM64R6-DAG: dmul $3, $5, $7 ; MM64R6-DAG: dmul $3, $5, $7
; MM32: lw $25, %call16(__multi3)($16) ; MM32: lw $25, %call16(__multi3)($gp)
%r = mul i128 %a, %b %r = mul i128 %a, %b
ret i128 %r ret i128 %r
} }

test/CodeGen/Mips/llvm-ir/sdiv.ll

Show First 20 Lines • Show All 166 Lines • ▼ Show 20 Lines; ALL-LABEL: sdiv_i64:
; GP64-NOT-R6: ddiv $zero, $4, $5 ; GP64-NOT-R6: ddiv $zero, $4, $5
; GP64-NOT-R6: teq $5, $zero, 7 ; GP64-NOT-R6: teq $5, $zero, 7
; GP64-NOT-R6: mflo $2 ; GP64-NOT-R6: mflo $2
; 64R6: ddiv $2, $4, $5 ; 64R6: ddiv $2, $4, $5
; 64R6: teq $5, $zero, 7 ; 64R6: teq $5, $zero, 7
; MM32: lw $25, %call16(__divdi3)($2) ; MM32: lw $25, %call16(__divdi3)($gp)
; MM64: ddiv $2, $4, $5 ; MM64: ddiv $2, $4, $5
; MM64: teq $5, $zero, 7 ; MM64: teq $5, $zero, 7
%r = sdiv i64 %a, %b %r = sdiv i64 %a, %b
ret i64 %r ret i64 %r
} }
define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) { define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: sdiv_i128: ; ALL-LABEL: sdiv_i128:
; ALL: l{{w|d}} $25, %call16(__divti3)($gp)
; GP32: lw $25, %call16(__divti3)($gp)
; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
; 64R6: ld $25, %call16(__divti3)($gp)
; MM32: lw $25, %call16(__divti3)($16)
; MM64: ld $25, %call16(__divti3)($2)
%r = sdiv i128 %a, %b %r = sdiv i128 %a, %b
ret i128 %r ret i128 %r
} }

test/CodeGen/Mips/llvm-ir/srem.ll

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines; ALL-LABEL: srem_i64:
; GP64-NOT-R6: ddiv $zero, $4, $5 ; GP64-NOT-R6: ddiv $zero, $4, $5
; GP64-NOT-R6: teq $5, $zero, 7 ; GP64-NOT-R6: teq $5, $zero, 7
; GP64-NOT-R6: mfhi $2 ; GP64-NOT-R6: mfhi $2
; 64R6: dmod $2, $4, $5 ; 64R6: dmod $2, $4, $5
; 64R6: teq $5, $zero, 7 ; 64R6: teq $5, $zero, 7
; MM32: lw $25, %call16(__moddi3)($2) ; MM32: lw $25, %call16(__moddi3)($gp)
; MM64: dmod $2, $4, $5 ; MM64: dmod $2, $4, $5
; MM64: teq $5, $zero, 7 ; MM64: teq $5, $zero, 7
%r = srem i64 %a, %b %r = srem i64 %a, %b
ret i64 %r ret i64 %r
} }
define signext i128 @srem_i128(i128 signext %a, i128 signext %b) { define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: srem_i128: ; ALL-LABEL: srem_i128:
; GP32: lw $25, %call16(__modti3)($gp) ; ALL: l{{w|d}} $25, %call16(__modti3)($gp)
; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
; 64R6: ld $25, %call16(__modti3)($gp)
; MM32: lw $25, %call16(__modti3)($16)
; MM64: ld $25, %call16(__modti3)($2)
%r = srem i128 %a, %b %r = srem i128 %a, %b
ret i128 %r ret i128 %r
} }

test/CodeGen/Mips/llvm-ir/udiv.ll

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines; ALL-LABEL: udiv_i64:
; GP64-NOT-R6: ddivu $zero, $4, $5 ; GP64-NOT-R6: ddivu $zero, $4, $5
; GP64-NOT-R6: teq $5, $zero, 7 ; GP64-NOT-R6: teq $5, $zero, 7
; GP64-NOT-R6: mflo $2 ; GP64-NOT-R6: mflo $2
; 64R6: ddivu $2, $4, $5 ; 64R6: ddivu $2, $4, $5
; 64R6: teq $5, $zero, 7 ; 64R6: teq $5, $zero, 7
; MM32: lw $25, %call16(__udivdi3)($2) ; MM32: lw $25, %call16(__udivdi3)($gp)
; MM64: ddivu $2, $4, $5 ; MM64: ddivu $2, $4, $5
; MM64: teq $5, $zero, 7 ; MM64: teq $5, $zero, 7
%r = udiv i64 %a, %b %r = udiv i64 %a, %b
ret i64 %r ret i64 %r
} }
define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) { define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: udiv_i128: ; ALL-LABEL: udiv_i128:
; GP32: lw $25, %call16(__udivti3)($gp) ; ALL: l{{w|d}} $25, %call16(__udivti3)($gp)
; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
; 64-R6: ld $25, %call16(__udivti3)($gp)
; MM32: lw $25, %call16(__udivti3)($16)
; MM64: ld $25, %call16(__udivti3)($2)
%r = udiv i128 %a, %b %r = udiv i128 %a, %b
ret i128 %r ret i128 %r
} }

test/CodeGen/Mips/llvm-ir/urem.ll

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines; ALL-LABEL: urem_i64:
; GP64-NOT-R6: ddivu $zero, $4, $5 ; GP64-NOT-R6: ddivu $zero, $4, $5
; GP64-NOT-R6: teq $5, $zero, 7 ; GP64-NOT-R6: teq $5, $zero, 7
; GP64-NOT-R6: mfhi $2 ; GP64-NOT-R6: mfhi $2
; 64R6: dmodu $2, $4, $5 ; 64R6: dmodu $2, $4, $5
; 64R6: teq $5, $zero, 7 ; 64R6: teq $5, $zero, 7
; MM32: lw $25, %call16(__umoddi3)($2) ; MM32: lw $25, %call16(__umoddi3)($gp)
; MM64: dmodu $2, $4, $5 ; MM64: dmodu $2, $4, $5
; MM64: teq $5, $zero, 7 ; MM64: teq $5, $zero, 7
%r = urem i64 %a, %b %r = urem i64 %a, %b
ret i64 %r ret i64 %r
} }
define signext i128 @urem_i128(i128 signext %a, i128 signext %b) { define signext i128 @urem_i128(i128 signext %a, i128 signext %b) {
entry: entry:
; ALL-LABEL: urem_i128: ; ALL-LABEL: urem_i128:
; GP32: lw $25, %call16(__umodti3)($gp) ; GP32: lw $25, %call16(__umodti3)($gp)
; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp)
; 64R6: ld $25, %call16(__umodti3)($gp) ; 64R6: ld $25, %call16(__umodti3)($gp)
; MM32: lw $25, %call16(__umodti3)($16) ; MM32: lw $25, %call16(__umodti3)($gp)
; MM64: ld $25, %call16(__umodti3)($2) ; MM64: ld $25, %call16(__umodti3)($gp)
%r = urem i128 %a, %b %r = urem i128 %a, %b
ret i128 %r ret i128 %r
} }

test/CodeGen/Mips/micromips-gp-rc.ll

; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
; RUN: -relocation-model=pic -O3 < %s | FileCheck %s ; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
@g = external global i32 @g = external global i32
; Function Attrs: noreturn nounwind ; Function Attrs: noreturn nounwind
define void @foo() #0 { define void @foo() #0 {
entry: entry:
%0 = load i32, i32* @g, align 4 %0 = load i32, i32* @g, align 4
tail call void @exit(i32 signext %0) tail call void @exit(i32 signext %0)
unreachable unreachable
} }
; Function Attrs: noreturn ; Function Attrs: noreturn
declare void @exit(i32 signext) declare void @exit(i32 signext)
; CHECK: move $gp, ${{[0-9]+}} ; CHECK: addu $gp, ${{[0-9]+}}

test/CodeGen/Mips/mips64fpldst.ll

; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 ; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 ; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 ; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 ; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 ; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N32
; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 ; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK-N64
@f0 = common global float 0.000000e+00, align 4 @f0 = common global float 0.000000e+00, align 4
@d0 = common global double 0.000000e+00, align 8 @d0 = common global double 0.000000e+00, align 8
@f1 = common global float 0.000000e+00, align 4 @f1 = common global float 0.000000e+00, align 4
@d1 = common global double 0.000000e+00, align 8 @d1 = common global double 0.000000e+00, align 8
define float @funcfl1() nounwind readonly { define float @funcfl1() nounwind readonly {
entry: entry:
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

test/CodeGen/Mips/tailcall/tailcall.ll

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines; PIC16: jalrc
ret i32 %call ret i32 %call
} }
define internal fastcc i32 @caller8_1() nounwind noinline { define internal fastcc i32 @caller8_1() nounwind noinline {
entry: entry:
; ALL-LABEL: caller8_1: ; ALL-LABEL: caller8_1:
; PIC32: jalr $25 ; PIC32: jalr $25
; PIC32R6: jalr $25 ; PIC32R6: jalr $25
; PIC32MM: jalr $25 ; PIC32MM: jalr{{.*}} $25
; STATIC32: jal ; STATIC32: jal
; PIC64: jalr $25 ; PIC64: jalr $25
; STATIC64: jal ; STATIC64: jal
; PIC16: jalrc ; PIC16: jalrc
%call = tail call i32 (i32, ...) @callee8(i32 2, i32 1) nounwind %call = tail call i32 (i32, ...) @callee8(i32 2, i32 1) nounwind
ret i32 %call ret i32 %call
} }
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
declare i32 @callee13(i32, ...) declare i32 @callee13(i32, ...)
define i32 @caller13() nounwind { define i32 @caller13() nounwind {
entry: entry:
; ALL-LABEL: caller13: ; ALL-LABEL: caller13:
; PIC32: jalr $25 ; PIC32: jalr $25
; PIC32R6: jalr $25 ; PIC32R6: jalr $25
; PIC32MM: jalr $25 ; PIC32MM: jalr{{.*}} $25
; STATIC32: jal ; STATIC32: jal
; STATIC64: jal ; STATIC64: jal
; PIC64R6: jalr $25 ; PIC64R6: jalr $25
; PIC64: jalr $25 ; PIC64: jalr $25
; PIC16: jalrc ; PIC16: jalrc
%call = tail call i32 (i32, ...) @callee13(i32 1, i32 2) nounwind %call = tail call i32 (i32, ...) @callee13(i32 1, i32 2) nounwind
ret i32 %call ret i32 %call
Show All 18 Lines