MachineRegisterInfo: Add way to mark individual registers as used

[arsenm]

Summary

There is already a way to add phys reg uses from a regmask,
but not for a single register.

This will help avoid fragile special handling in AMDGPU
reserved register compaction code in the prolog handling.

[MatzeB]

I think UsedPhysRegMask is supposed to be the union of all register mask operands in the function. It just functions as a cache there. Having a way to manually set/reset it seems wrong to me. What exactly do you want/need this for?

[arsenm]

In D31955#725230, @MatzeB wrote:

I think UsedPhysRegMask is supposed to be the union of all register mask operands in the function. It just functions as a cache there. Having a way to manually set/reset it seems wrong to me. What exactly do you want/need this for?

The code before was replacing uses of reserved registers before the uses were added. I reordered things so I think that this isn't necessary anymore

include/llvm/CodeGen/MachineRegisterInfo.h

#endif
   bool isPhysRegUsed(unsigned PhysReg) const;
 
   /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
   /// This corresponds to the bit mask attached to register mask operands.
   void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
     UsedPhysRegMask.setBitsNotInMask(RegMask);
   }
 
+  /// Mark \p Reg and any aliases of it as used.
+  void addPhysRegUsed(const TargetRegisterInfo &TRI, unsigned Reg) {
+    MCRegAliasIterator R(Reg, &TRI, true);
+    for (; R.isValid(); ++R)
+      UsedPhysRegMask.set(*R);
+  }
+
   const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
 
   //===--------------------------------------------------------------------===//
   // Reserved Register Info
   //===--------------------------------------------------------------------===//
   //
   // The set of reserved registers must be invariant during register
   // allocation.  For example, the target cannot suddenly decide it needs a