Separate {Min,Max}AtomicLockFreeWidth from MaxAtomicInlineWidth

[sunfish]

Summary

Currently, clang uses the MaxAtomicInlineWidth to determine both whether atomics up to a certain size can be "inlined" (aka, not a libcall), and also whether those atomics are guaranteed to be always lock-free. This implicitly assumes that if, for example, a 32-bit atomic is guaranteed lock free, that 16-bit and 8-bit are also guaranteed lock free, because they're also less than the maximum.

WebAssembly's proposed design for atomics has a guarantee that 4-byte atomics are always lock-free, but not 2-byte or 1-byte atomics. One reason is that on MIPS at least, it's not clear from available documentation that doing a 32-bit ll+sc sequence to implement an 8-bit or 16-bit atomic is safe if there's a possibility that a non-atomic access could concurrently modify any of the other 24 or 16 bits, respectively.

Clang on MIPS uses ll+sc to implement 8-bit and 16-bit atomics, and declares that they are lock-free (as they are within the MaxAtomicInlineWidth). It appears to do similar things on other targets.

Does clang know that this is always safe to do on MIPS and other targets? If there's documentation guaranteeing this, it would be desirable to feed this information back to the WebAssembly community so that the atomics proposal can be updated to reflect this.

Alternatively, if it's not safe, the attached patch may be useful. It introduces MinAtomicLockFreeWidth and MaxAtomicLockFreeWidth and uses it in the WebAssembly target to limit it to only 32-bit lock-free atomics. Possibly it would be appropriate to make MIPS and other targets use this too, however I have not yet made such changes.

[efriedma]

Not sure what MIPS reference you're looking at; the ones I can find say something like this: "If either of the following events occurs between the execution of LL and SC, the SC fails: A coherent store is completed by another processor or coherent I/O module into the block of synchronizable physical memory containing the word. The size and alignment of the block is implementation-dependent, but it is at least one word and at most the minimum page size. [...]"

The ARM architecture reference has a detailed description of semantics of the local and global monitors; the global monitor protects a block of memory of at least 8 bytes.

[sunfish]

The perspective from the folks designing the WebAssembly memory model is that

• WebAssembly has greater backwards-compatibility requirements than LLVM does, so it needs to be more conservative, in general.
• 1-byte and 2-byte atomic operations aren't very important.

Consequently, WebAssembly intends to retain the property that 4-byte atomics are guaranteed lock-free, and 2-byte and 1-byte are not guaranteed. To implement this in clang, we'll need something like the patch here.

[joerg]

I don't get this. If you have a lock-free 32bit CAS, you can implement all the 16bit operations on top of that and they are still lock-free.

[sunfish]

There could conceivably be CPUs where 32-bit CAS is not the most efficient way to implement an 8-bit or 16-bit atomic operation. The other assumption is that 8-bit and 16-bit are much less important here, so the benefit of making the guarantee isn't seen to be worth the risks at this time. With backwards compatibility, one can always add guarantees that turn out to be useful in the future, but not remove guarantees that turn out to be harmful.

For further questions, I encourage you to file an issue at the threads proposal repository. The proposed lock-free guarantee is currently stated here.

[joerg]

Lock-free operations provide two major advantages. You don't need to worry about signal safety and they can be mixed with certain non-atomic operations without creating havoc. All I said is that the presence of a 32bit CAS is enough to ensure lock-free atomic operations for (appropriately aligned) 8bit and 16bit values can be implemented. That will not be worse than any locked atomic operation on any non-brain-dead platform. E.g. it might not be true on SPARC v7 and v8 or the VAX, but then they don't have a 32bit CAS. It doesn't mean that you have to implement 16bit atomics using a 32bit CAS. I would hope the webassembly backend exposes atomics as precise operations, but if it only provides a 32bit CAS, that's still good enough for the needs of any frontend language.

[sunfish]

If you believe the WebAssembly design is unreasonable, please do file an issue. The memory model is just a proposal right now and can be changed.

Otherwise, this is how the platform works. It has 8-bit and 16-bit atomics, and they are not guaranteed lock-free. LLVM's main options seem to be: accept this patch, use 32-bit CAS for all 8-bit and 16-bit atomics in wasm and be inefficient on hardware that does have real 8-bit and 16-bit atomics, or be buggy.

[sunfish]

From the discussion at the recent WebAssembly CG meeting, it seems likely that the shared memory proposal will be modified such that this patch will no longer be needed. Closing.

include/clang/Basic/TargetInfo.h

protected:
   unsigned char LongDoubleWidth, LongDoubleAlign, Float128Align;
   unsigned char LargeArrayMinWidth, LargeArrayAlign;
   unsigned char LongWidth, LongAlign;
   unsigned char LongLongWidth, LongLongAlign;
   unsigned char SuitableAlign;
   unsigned char DefaultAlignForAttributeAligned;
   unsigned char MinGlobalAlign;
   unsigned char MaxAtomicPromoteWidth, MaxAtomicInlineWidth;
+  unsigned char MinAtomicLockFreeWidth, MaxAtomicLockFreeWidth;
   unsigned short MaxVectorAlign;
   unsigned short MaxTLSAlign;
   unsigned short SimdDefaultAlign;
   unsigned short NewAlign;
   std::unique_ptr<llvm::DataLayout> DataLayout;
   const char *MCountName;
   const llvm::fltSemantics *HalfFormat, *FloatFormat, *DoubleFormat,
     *LongDoubleFormat, *Float128Format;
public:
   // getLargeArrayMinWidth/Align - Return the minimum array size that is
   // 'large' and its alignment.
   unsigned getLargeArrayMinWidth() const { return LargeArrayMinWidth; }
   unsigned getLargeArrayAlign() const { return LargeArrayAlign; }
 
   /// \brief Return the maximum width lock-free atomic operation which will
   /// ever be supported for the given target
   unsigned getMaxAtomicPromoteWidth() const { return MaxAtomicPromoteWidth; }
-  /// \brief Return the maximum width lock-free atomic operation which can be
-  /// inlined given the supported features of the given target.
+  /// \brief Return the maximum width atomic operation which can be inlined
+  /// given the supported features of the given target.
   unsigned getMaxAtomicInlineWidth() const { return MaxAtomicInlineWidth; }
-  /// \brief Returns true if the given target supports lock-free atomic
+  /// \brief Return the minimum width lock-free atomic operation which can be
+  /// supported given the supported features of the given target.
+  unsigned getMinAtomicLockFreeWidth() const { return MinAtomicLockFreeWidth; }
+  /// \brief Return the maximum width lock-free atomic operation which can be
+  /// supported given the supported features of the given target.
+  unsigned getMaxAtomicLockFreeWidth() const { return MaxAtomicLockFreeWidth; }
+  /// \brief Returns true if the given target supports inline atomic
   /// operations at the specified width and alignment.
   virtual bool hasBuiltinAtomic(uint64_t AtomicSizeInBits,
                                 uint64_t AlignmentInBits) const {
     return AtomicSizeInBits <= AlignmentInBits &&
            AtomicSizeInBits <= getMaxAtomicInlineWidth() &&
            (AtomicSizeInBits <= getCharWidth() ||
             llvm::isPowerOf2_64(AtomicSizeInBits / getCharWidth()));
   }

lib/AST/ExprConstant.cpp

bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E,
   case Builtin::BI__atomic_always_lock_free:
   case Builtin::BI__atomic_is_lock_free:
   case Builtin::BI__c11_atomic_is_lock_free: {
     APSInt SizeVal;
     if (!EvaluateInteger(E->getArg(0), SizeVal, Info))
       return false;
 
     // For __atomic_is_lock_free(sizeof(_Atomic(T))), if the size is a power
-    // of two less than the maximum inline atomic width, we know it is
+    // of two less than the maximum lock-free atomic width, we know it is
     // lock-free.  If the size isn't a power of two, or greater than the
     // maximum alignment where we promote atomics, we know it is not lock-free
     // (at least not in the sense of atomic_is_lock_free).  Otherwise,
     // the answer can only be determined at runtime; for example, 16-byte
     // atomics have lock-free implementations on some, but not all,
     // x86-64 processors.
 
     // Check power-of-two.
     CharUnits Size = CharUnits::fromQuantity(SizeVal.getZExtValue());
     if (Size.isPowerOfTwo()) {
-      // Check against inlining width.
-      unsigned InlineWidthBits =
-          Info.Ctx.getTargetInfo().getMaxAtomicInlineWidth();
-      if (Size <= Info.Ctx.toCharUnitsFromBits(InlineWidthBits)) {
+      // Check against lock-free width.
+      unsigned MinLockFreeWidthBits =
+          Info.Ctx.getTargetInfo().getMinAtomicLockFreeWidth();
+      unsigned MaxLockFreeWidthBits =
+          Info.Ctx.getTargetInfo().getMaxAtomicLockFreeWidth();
+      if (Size >= Info.Ctx.toCharUnitsFromBits(MinLockFreeWidthBits) &&
+          Size <= Info.Ctx.toCharUnitsFromBits(MaxLockFreeWidthBits)) {
         if (BuiltinOp == Builtin::BI__c11_atomic_is_lock_free ||
             Size == CharUnits::One() ||
             E->getArg(1)->isNullPointerConstant(Info.Ctx,
                                                 Expr::NPC_NeverValueDependent))
-          // OK, we will inline appropriately-aligned operations of this size,
-          // and _Atomic(T) is appropriately-aligned.
+          // OK, appropriately-aligned operations of this size will be
+          // lock-free, and _Atomic(T) is appropriately-aligned.
           return Success(1, E);
 
         QualType PointeeType = E->getArg(1)->IgnoreImpCasts()->getType()->
           castAs<PointerType>()->getPointeeType();
         if (!PointeeType->isIncompleteType() &&
             Info.Ctx.getTypeAlignInChars(PointeeType) >= Size) {
-          // OK, we will inline operations on this object.
+          // OK, operations on this object will be lock-free.
           return Success(1, E);
         }
       }
     }
 
     return BuiltinOp == Builtin::BI__atomic_always_lock_free ?
         Success(0, E) : Error(E);
   }

lib/Basic/TargetInfo.cpp

TargetInfo::TargetInfo(const llvm::Triple &T) : TargetOpts(), Triple(T) {
   DoubleWidth = 64;
   DoubleAlign = 64;
   LongDoubleWidth = 64;
   LongDoubleAlign = 64;
   Float128Align = 128;
   LargeArrayMinWidth = 0;
   LargeArrayAlign = 0;
   MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 0;
+  MinAtomicLockFreeWidth = MaxAtomicLockFreeWidth = 0;
   MaxVectorAlign = 0;
   MaxTLSAlign = 0;
   SimdDefaultAlign = 0;
   SizeType = UnsignedLong;
   PtrDiffType = SignedLong;
   IntMaxType = SignedLongLong;
   IntPtrType = SignedLong;
   WCharType = SignedInt;

lib/Basic/Targets.cpp

PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
     }
 
     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
       LongDoubleWidth = LongDoubleAlign = 64;
       LongDoubleFormat = &llvm::APFloat::IEEEdouble();
     }
 
     // PPC32 supports atomics up to 4 bytes.
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
+    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 32;
   }
 
   BuiltinVaListKind getBuiltinVaListKind() const override {
     // This is the ELF definition, and is overridden by the Darwin sub-target
     return TargetInfo::PowerABIBuiltinVaList;
   }
 };
 
case llvm::Triple::NetBSD:
       IntMaxType = SignedLongLong;
       Int64Type = SignedLongLong;
       break;
     default:
       break;
     }
 
     // PPC64 supports atomics up to 8 bytes.
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 64;
   }
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::CharPtrBuiltinVaList;
   }
   // PPC64 Linux-specific ABI options.
   bool setABI(const std::string &Name) override {
     if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
       ABI = Name;
NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts,
     UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment();
     ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary();
 
     // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and
     // we need those macros to be identical on host and device, because (among
     // other things) they affect which standard library classes are defined, and
     // we need all classes to be defined on both the host and device.
     MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth();
+    MinAtomicLockFreeWidth = HostTarget->getMinAtomicLockFreeWidth();
+    MaxAtomicLockFreeWidth = HostTarget->getMaxAtomicLockFreeWidth();
 
     // Properties intentionally not copied from host:
     // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the
     //   host/device boundary.
     // - SuitableAlign: Not visible across the host/device boundary, and may
     //   correctly be different on host/device, e.g. if host has wider vector
     //   types than device.
     // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same
X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
     // Use fpret for all types.
     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
                              (1 << TargetInfo::Double) |
                              (1 << TargetInfo::LongDouble));
 
     // x86-32 has atomics up to 8 bytes
     // FIXME: Check that we actually have cmpxchg8b before setting
     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 64;
   }
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::CharPtrBuiltinVaList;
   }
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
     if (RegNo == 0) return 0;
     if (RegNo == 1) return 2;
X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
     ComplexLongDoubleUsesFP2Ret = true;
 
     // Make __builtin_ms_va_list available.
     HasBuiltinMSVaList = true;
 
     // x86-64 has atomics up to 16 bytes.
     MaxAtomicPromoteWidth = 128;
     MaxAtomicInlineWidth = 128;
+    MaxAtomicLockFreeWidth = 128;
   }
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::X86_64ABIBuiltinVaList;
   }
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
     if (RegNo == 0) return 0;
     if (RegNo == 1) return 1;
void setAtomic() {
     // then we are not using inline atomics
     bool ShouldUseInlineAtomic =
                    (ArchISA == llvm::ARM::IK_ARM   && ArchVersion >= 6) ||
                    (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
     if (ArchProfile == llvm::ARM::PK_M) {
       MaxAtomicPromoteWidth = 32;
       if (ShouldUseInlineAtomic)
-        MaxAtomicInlineWidth = 32;
+        MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 32;
     }
     else {
       MaxAtomicPromoteWidth = 64;
       if (ShouldUseInlineAtomic)
-        MaxAtomicInlineWidth = 64;
+        MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 64;
     }
   }
 
   bool isThumb() const {
     return (ArchISA == llvm::ARM::IK_THUMB);
   }
 
   bool supportsThumb() const {

 
 public:
   DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
       : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) {
     HasAlignMac68kSupport = true;
     // iOS always has 64-bit atomic instructions.
     // FIXME: This should be based off of the target features in
     // ARMleTargetInfo.
-    MaxAtomicInlineWidth = 64;
+    MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 64;
 
     if (Triple.isWatchABI()) {
       // Darwin on iOS uses a variant of the ARM C++ ABI.
       TheCXXABI.set(TargetCXXABI::WatchOS);
 
       // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
       // size_t is long, it's a bit weird for it to be int.
       PtrDiffType = SignedLong;
if (getTriple().getOS() == llvm::Triple::NetBSD ||
       Int64Type = SignedLong;
       IntMaxType = SignedLong;
     }
 
     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
     MaxVectorAlign = 128;
     MaxAtomicInlineWidth = 128;
     MaxAtomicPromoteWidth = 128;
+    MaxAtomicLockFreeWidth = 128;
 
     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
     LongDoubleFormat = &llvm::APFloat::IEEEquad();
 
     // {} in inline assembly are neon specifiers, not assembly variant
     // specifiers.
     NoAsmVariants = true;
 
case llvm::Triple::OpenBSD:
       IntPtrType = SignedLong;
       PtrDiffType = SignedLong;
       break;
     }
     // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops
     // on up to 64 bits.
     MaxAtomicPromoteWidth = 64;
     MaxAtomicInlineWidth = 32;
+    MaxAtomicLockFreeWidth = 32;
   }
 
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override {
     SparcTargetInfo::getTargetDefines(Opts, Builder);
     switch (getCPUGeneration(CPU)) {
     case CG_V8:
       Builder.defineMacro("__sparcv8");
else
       IntMaxType = SignedLong;
     Int64Type = IntMaxType;
 
     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
     LongDoubleWidth = 128;
     LongDoubleAlign = 128;
     LongDoubleFormat = &llvm::APFloat::IEEEquad();
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 64;
   }
 
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override {
     SparcTargetInfo::getTargetDefines(Opts, Builder);
     Builder.defineMacro("__sparcv9");
     Builder.defineMacro("__arch64__");
     // Solaris doesn't need these variants, but the BSDs do.
SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
     PointerWidth = PointerAlign = 64;
     LongDoubleWidth = 128;
     LongDoubleAlign = 64;
     LongDoubleFormat = &llvm::APFloat::IEEEquad();
     DefaultAlignForAttributeAligned = 64;
     MinGlobalAlign = 16;
     resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64");
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 64;
   }
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override {
     Builder.defineMacro("__s390__");
     Builder.defineMacro("__s390x__");
     Builder.defineMacro("__zarch__");
     Builder.defineMacro("__LONG_DOUBLE_128__");
 
BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
     RegParmMax = 5;
     if (Triple.getArch() == llvm::Triple::bpfeb) {
       resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128");
     } else {
       resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
     }
     MaxAtomicPromoteWidth = 64;
     MaxAtomicInlineWidth = 64;
+    MaxAtomicLockFreeWidth = 64;
     TLSSupported = false;
   }
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override {
     DefineStd(Builder, "bpf", Opts);
     Builder.defineMacro("__BPF__");
   }
   bool hasFeature(StringRef Feature) const override {
public:
   }
 
   void setO32ABITypes() {
     Int64Type = SignedLongLong;
     IntMaxType = Int64Type;
     LongDoubleFormat = &llvm::APFloat::IEEEdouble();
     LongDoubleWidth = LongDoubleAlign = 64;
     LongWidth = LongAlign = 32;
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
+    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 32;
     PointerWidth = PointerAlign = 32;
     PtrDiffType = SignedInt;
     SizeType = UnsignedInt;
     SuitableAlign = 64;
   }
 
   void setN32N64ABITypes() {
     LongDoubleWidth = LongDoubleAlign = 128;
     LongDoubleFormat = &llvm::APFloat::IEEEquad();
     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
       LongDoubleWidth = LongDoubleAlign = 64;
       LongDoubleFormat = &llvm::APFloat::IEEEdouble();
     }
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 64;
     SuitableAlign = 128;
   }
 
   void setN64ABITypes() {
     setN32N64ABITypes();
     if (getTriple().getOS() == llvm::Triple::OpenBSD) {
       Int64Type = SignedLongLong;
     } else {

 class Le64TargetInfo : public TargetInfo {
   static const Builtin::Info BuiltinInfo[];
 
 public:
   Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
       : TargetInfo(Triple) {
     NoAsmVariants = true;
     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 64;
     resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128");
   }
 
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override {
     DefineStd(Builder, "unix", Opts);
     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
     Builder.defineMacro("__ELF__");

 #include "clang/Basic/BuiltinsWebAssembly.def"
 };
 
 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
 public:
   explicit WebAssembly32TargetInfo(const llvm::Triple &T,
                                    const TargetOptions &Opts)
       : WebAssemblyTargetInfo(T, Opts) {
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
+    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 32;
+
+    // WebAssembly only guarantees that 32-bit atomics are lock free, and not
+    // other sizes (including smaller sizes).
+    MinAtomicLockFreeWidth = 32;
+
     resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128");
   }
 
 protected:
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override {
     WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
     defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
   }
 };
 
 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
 public:
   explicit WebAssembly64TargetInfo(const llvm::Triple &T,
                                    const TargetOptions &Opts)
       : WebAssemblyTargetInfo(T, Opts) {
     LongAlign = LongWidth = 64;
     PointerAlign = PointerWidth = 64;
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = MaxAtomicLockFreeWidth = 64;
+
+    // WebAssembly only guarantees that 32-bit atomics are lock free, and not
+    // other sizes (including smaller sizes).
+    MinAtomicLockFreeWidth = 32;
+
     SizeType = UnsignedLong;
     PtrDiffType = SignedLong;
     IntPtrType = SignedLong;
     resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128");
   }
 
 protected:
   void getTargetDefines(const LangOptions &Opts,

lib/Frontend/InitPreprocessor.cpp

static void DefineFastIntType(unsigned TypeWidth, bool IsSigned,
 
   DefineFmt(Prefix + Twine(TypeWidth), Ty, TI, Builder);
 }
 
 
 /// Get the value the ATOMIC_*_LOCK_FREE macro should have for a type with
 /// the specified properties.
 static const char *getLockFreeValue(unsigned TypeWidth, unsigned TypeAlign,
-                                    unsigned InlineWidth) {
-  // Fully-aligned, power-of-2 sizes no larger than the inline
+                                    unsigned MinLockFreeWidth,
+                                    unsigned MaxLockFreeWidth) {
+  // Fully-aligned, power-of-2 sizes no larger than the lock-free
   // width will be inlined as lock-free operations.
   if (TypeWidth == TypeAlign && (TypeWidth & (TypeWidth - 1)) == 0 &&
-      TypeWidth <= InlineWidth)
+      TypeWidth >= MinLockFreeWidth && TypeWidth <= MaxLockFreeWidth)
     return "2"; // "always lock free"
   // We cannot be certain what operations the lib calls might be
   // able to implement as lock-free on future processors.
   return "1"; // "sometimes lock free"
 }
 
 /// \brief Add definitions required for a smooth interaction between
 /// Objective-C++ automated reference counting and libstdc++ (4.2).
if (!LangOpts.MSVCCompat) {
     else
       Builder.defineMacro("__GNUC_STDC_INLINE__");
 
     // The value written by __atomic_test_and_set.
     // FIXME: This is target-dependent.
     Builder.defineMacro("__GCC_ATOMIC_TEST_AND_SET_TRUEVAL", "1");
 
     // Used by libc++ and libstdc++ to implement ATOMIC_<foo>_LOCK_FREE.
-    unsigned InlineWidthBits = TI.getMaxAtomicInlineWidth();
+    unsigned MaxLockFreeWidthBits = TI.getMaxAtomicLockFreeWidth();
+    unsigned MinLockFreeWidthBits = TI.getMinAtomicLockFreeWidth();
 #define DEFINE_LOCK_FREE_MACRO(TYPE, Type) \
     Builder.defineMacro("__GCC_ATOMIC_" #TYPE "_LOCK_FREE", \
                         getLockFreeValue(TI.get##Type##Width(), \
                                          TI.get##Type##Align(), \
-                                         InlineWidthBits));
+                                         MinLockFreeWidthBits, \
+                                         MaxLockFreeWidthBits));
     DEFINE_LOCK_FREE_MACRO(BOOL, Bool);
     DEFINE_LOCK_FREE_MACRO(CHAR, Char);
     DEFINE_LOCK_FREE_MACRO(CHAR16_T, Char16);
     DEFINE_LOCK_FREE_MACRO(CHAR32_T, Char32);
     DEFINE_LOCK_FREE_MACRO(WCHAR_T, WChar);
     DEFINE_LOCK_FREE_MACRO(SHORT, Short);
     DEFINE_LOCK_FREE_MACRO(INT, Int);
     DEFINE_LOCK_FREE_MACRO(LONG, Long);
     DEFINE_LOCK_FREE_MACRO(LLONG, LongLong);
     Builder.defineMacro("__GCC_ATOMIC_POINTER_LOCK_FREE",
                         getLockFreeValue(TI.getPointerWidth(0),
                                          TI.getPointerAlign(0),
-                                         InlineWidthBits));
+                                         MinLockFreeWidthBits,
+                                         MaxLockFreeWidthBits));
 #undef DEFINE_LOCK_FREE_MACRO
   }
 
   if (LangOpts.NoInlineDefine)
     Builder.defineMacro("__NO_INLINE__");
 
   if (unsigned PICLevel = LangOpts.PICLevel) {
     Builder.defineMacro("__PIC__", Twine(PICLevel));

test/Preprocessor/init.c

 // WEBASSEMBLY32-NEXT:#define __FLT_MANT_DIG__ 24
 // WEBASSEMBLY32-NEXT:#define __FLT_MAX_10_EXP__ 38
 // WEBASSEMBLY32-NEXT:#define __FLT_MAX_EXP__ 128
 // WEBASSEMBLY32-NEXT:#define __FLT_MAX__ 3.40282347e+38F
 // WEBASSEMBLY32-NEXT:#define __FLT_MIN_10_EXP__ (-37)
 // WEBASSEMBLY32-NEXT:#define __FLT_MIN_EXP__ (-125)
 // WEBASSEMBLY32-NEXT:#define __FLT_MIN__ 1.17549435e-38F
 // WEBASSEMBLY32-NEXT:#define __FLT_RADIX__ 2
-// WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_BOOL_LOCK_FREE 2
-// WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_BOOL_LOCK_FREE 1
+// WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 1
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
-// WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_CHAR_LOCK_FREE 1
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_INT_LOCK_FREE 2
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_LLONG_LOCK_FREE 1
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_LONG_LOCK_FREE 2
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_POINTER_LOCK_FREE 2
-// WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_SHORT_LOCK_FREE 1
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // WEBASSEMBLY32-NEXT:#define __GNUC_MINOR__ {{.*}}
 // WEBASSEMBLY32-NEXT:#define __GNUC_PATCHLEVEL__ {{.*}}
 // WEBASSEMBLY32-NEXT:#define __GNUC_STDC_INLINE__ 1
 // WEBASSEMBLY32-NEXT:#define __GNUC__ {{.*}}
 // WEBASSEMBLY32-NEXT:#define __GXX_ABI_VERSION 1002
 // WEBASSEMBLY32-NEXT:#define __ILP32__ 1

 // WEBASSEMBLY64-NEXT:#define __FLT_MANT_DIG__ 24
 // WEBASSEMBLY64-NEXT:#define __FLT_MAX_10_EXP__ 38
 // WEBASSEMBLY64-NEXT:#define __FLT_MAX_EXP__ 128
 // WEBASSEMBLY64-NEXT:#define __FLT_MAX__ 3.40282347e+38F
 // WEBASSEMBLY64-NEXT:#define __FLT_MIN_10_EXP__ (-37)
 // WEBASSEMBLY64-NEXT:#define __FLT_MIN_EXP__ (-125)
 // WEBASSEMBLY64-NEXT:#define __FLT_MIN__ 1.17549435e-38F
 // WEBASSEMBLY64-NEXT:#define __FLT_RADIX__ 2
-// WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_BOOL_LOCK_FREE 2
-// WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_BOOL_LOCK_FREE 1
+// WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 1
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
-// WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_CHAR_LOCK_FREE 1
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_INT_LOCK_FREE 2
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_LLONG_LOCK_FREE 2
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_LONG_LOCK_FREE 2
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_POINTER_LOCK_FREE 2
-// WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_SHORT_LOCK_FREE 1
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // WEBASSEMBLY64-NEXT:#define __GNUC_MINOR__ {{.*}}
 // WEBASSEMBLY64-NEXT:#define __GNUC_PATCHLEVEL__ {{.*}}
 // WEBASSEMBLY64-NEXT:#define __GNUC_STDC_INLINE__ 1
 // WEBASSEMBLY64-NEXT:#define __GNUC__ {{.}}
 // WEBASSEMBLY64-NEXT:#define __GXX_ABI_VERSION 1002
 // WEBASSEMBLY64-NOT:#define __ILP32__