Allow targets to opt-in to codegen in SCC order

[arsenm]

Summary

Decouple this setting from EnableIRPA.

To support function calls on AMDGPU, it is necessary to
report the global register usage throughout the kernel's
call graph, so callees need to be handled first.

[arsenm]

Fix missing piece

[MatzeB]

I'd lean towards putting the option into TargetPassConfig instead of TargetMachine, what do you think?

[arsenm]

In D31512#718333, @MatzeB wrote:

I'd lean towards putting the option into TargetPassConfig instead of TargetMachine, what do you think?

I wasn't sure on this. Is there any reason passes would need to check this? If not, then TargetPassConfig is probably the right place.

[MatzeB]

In D31512#718347, @arsenm wrote:

In D31512#718333, @MatzeB wrote:

I'd lean towards putting the option into TargetPassConfig instead of TargetMachine, what do you think?

I wasn't sure on this. Is there any reason passes would need to check this? If not, then TargetPassConfig is probably the right place.

I can't think of a reason why passes would want to know this (and they certainly shouldn't rely on a specific order).

[arsenm]

Move to TargetPassConfig

[MatzeB]

LGTM

[arsenm]

r299487

include/llvm/Target/TargetMachine.h

protected: // Can only create subclasses.
   /// Contains target specific asm information.
   const MCAsmInfo *AsmInfo;
 
   const MCRegisterInfo *MRI;
   const MCInstrInfo *MII;
   const MCSubtargetInfo *STI;
 
   unsigned RequireStructuredCFG : 1;
+  unsigned RequireCodeGenSCCOrder : 1;
   unsigned O0WantsFastISel : 1;
 
 public:
   const TargetOptions DefaultOptions;
   mutable TargetOptions Options;
 
   TargetMachine(const TargetMachine &) = delete;
   void operator=(const TargetMachine &) = delete;
public:
   /// If intrinsic information is available, return it.  If not, return null.
   virtual const TargetIntrinsicInfo *getIntrinsicInfo() const {
     return nullptr;
   }
 
   bool requiresStructuredCFG() const { return RequireStructuredCFG; }
   void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; }
 
+  bool requiresCodeGenSCCOrder() const { return RequireCodeGenSCCOrder; }
+  void setRequiresCodeGenSCCOrder(bool Value) { RequireCodeGenSCCOrder = Value; }
+
   /// Returns the code generation relocation model. The choices are static, PIC,
   /// and dynamic-no-pic, and target default.
   Reloc::Model getRelocationModel() const;
 
   /// Returns the code model. The choices are small, kernel, medium, large, and
   /// target default.
   CodeModel::Model getCodeModel() const;
 

lib/CodeGen/TargetPassConfig.cpp

 }
 
 /// Add common passes that perform LLVM IR to IR transforms in preparation for
 /// instruction selection.
 void TargetPassConfig::addISelPrepare() {
   addPreISel();
 
   // Force codegen to run according to the callgraph.
-  if (TM->Options.EnableIPRA)
+  if (TM->requiresCodeGenSCCOrder())
     addPass(new DummyCGSCCPass);
 
   // Add both the safe stack and the stack protection passes: each of them will
   // only protect functions that have corresponding attributes.
   addPass(createSafeStackPass(TM));
   addPass(createStackProtectorPass(TM));
 
   if (PrintISelInput)