[Thumb1] combine ADDC/SUBC with a negative immediate

[tyomitch]

Summary

This simple optimization has been split out of https://reviews.llvm.org/D30400

[rengolin]

Can you make sure this works with inline asm? We had a trick in the to make it work (Linux stuff), so I just want to make sure it follows the same path on both cases.

[tyomitch]

Can you make sure this works with inline asm? We had a trick in the to make it work (Linux stuff)

Can you suggest a test case? I'm not quite sure how ADDC/SUBC, inline asm, and Linux all relate to each other.

[rengolin]

Right, sorry, this has nothing to do with the assembler, and is only to perform better codegen. Ignore my comments. LGTM. Thanks!

[zzheng]

This patch needs to be reverted or appended. I'll try to send a test case.

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

9794

There's a corner case when imm is -2147483648, that's -2^31 and 0x80000000 in two's compliment.

SignExt this value and flip its sign in int64_t, it's still 0x80000000 and interpreted as -2^31 by i32 type.

So we have infinite loop here where this function consume and produce the same node forever.

[zzheng]

This test case reproduce the problem (infinite compile time)

define i64 @f6(i64 %x, i64 %y) {
entry:

%tmp1 = add i64 %y, -2147483648           ; <i64> [#uses=1]
ret i64 %tmp1

}

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

else
     return SDValue();
 }
 
 static SDValue PerformAddcSubcCombine(SDNode *N, SelectionDAG &DAG,
                                       const ARMSubtarget *Subtarget) {
   if (Subtarget->isThumb1Only()) {
     SDValue RHS = N->getOperand(1);
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
-      int64_t imm = C->getSExtValue();
-      if (imm < 0) {
+      int32_t imm = C->getSExtValue();
+      if (-imm > 0) {
         SDLoc DL(N);
         RHS = DAG.getConstant(-imm, DL, MVT::i32);
         unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC
                                                            : ARMISD::ADDC;
         return DAG.getNode(Opcode, DL, N->getVTList(), N->getOperand(0), RHS);
       }
     }
   }
   return SDValue();
 }
 
 static SDValue PerformAddeSubeCombine(SDNode *N, SelectionDAG &DAG,
                                       const ARMSubtarget *Subtarget) {
   if (Subtarget->isThumb1Only()) {
     SDValue RHS = N->getOperand(1);
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
-      int64_t imm = C->getSExtValue();
-      if (imm < 0) {
+      int32_t imm = C->getSExtValue();
+      if (-imm > 0) {
         SDLoc DL(N);
 
         // The with-carry-in form matches bitwise not instead of the negation.
         // Effectively, the inverse interpretation of the carry flag already
         // accounts for part of the negation.
         RHS = DAG.getConstant(~imm, DL, MVT::i32);
 
         unsigned Opcode = (N->getOpcode() == ARMISD::ADDE) ? ARMISD::SUBE

llvm/trunk/test/CodeGen/Thumb/long.ll

 ; CHECK: movs r1, #0
 ; CHECK: subs r2, r2, r0
 ; CHECK: sbcs r3, r1
 ; CHECK: subs r0, r2, r0
 ; CHECK: sbcs r3, r1
 ; CHECK: movs r1, r3
 }
 
+; "sub 2147483648" has to be lowered into "add -2147483648"
+define i64 @f12(i64 %x, i64 %y) {
+entry:
+        %tmp1 = sub i64 %x, 2147483648
+        ret i64 %tmp1
+; CHECK-LABEL: f12:
+; CHECK: movs r2, #1
+; CHECK: lsls r2, r2, #31
+; CHECK: movs r3, #0
+; CHECK: adds r0, r0, r2
+; CHECK: sbcs r1, r3
+}