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Differential D30554

[AArch64] Extend redundant copy elimination pass to handle shifted compares.
AbandonedPublic

Authored by mcrosier on Mar 2 2017, 2:32 PM.

Details

Reviewers
gberry
MatzeB
Summary

Please take a look.

Chad

Diff Detail

Revision Contents

PathSize
lib/
Target/
AArch64/
8 lines
test/
CodeGen/
AArch64/
25 lines

Diff 90397

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Lines for (MachineInstr &PredI : make_range(std::next(RIt), PredMBB->rend())) {
// CMP is an alias for SUBS with a dead destination register. // CMP is an alias for SUBS with a dead destination register.
case AArch64::SUBSWri: case AArch64::SUBSWri:
case AArch64::SUBSXri: { case AArch64::SUBSXri: {
unsigned SrcReg = PredI.getOperand(1).getReg(); unsigned SrcReg = PredI.getOperand(1).getReg();
// Must not be a symbolic immediate. // Must not be a symbolic immediate.
if (!PredI.getOperand(2).isImm()) if (!PredI.getOperand(2).isImm())
return None; return None;
// FIXME: For simplicity, give up on non-zero shifts.
if (PredI.getOperand(3).getImm())
return None;
// The src register must not be modified between the cmp and conditional // The src register must not be modified between the cmp and conditional
// branch. This includes a self-clobbering compare. // branch. This includes a self-clobbering compare.
if (ClobberedRegs[SrcReg]) if (ClobberedRegs[SrcReg])
return None; return None;
// We've found the Cmp that sets NZCV. // We've found the Cmp that sets NZCV.
int32_t Imm = PredI.getOperand(2).getImm();
int32_t Shift = PredI.getOperand(3).getImm();
FirstUse = PredI; FirstUse = PredI;
return RegImm(PredI.getOperand(1).getReg(), PredI.getOperand(2).getImm()); return RegImm(PredI.getOperand(1).getReg(), Imm << Shift);
} }
} }
// Bail if we see an instruction that defines NZCV that we don't handle. // Bail if we see an instruction that defines NZCV that we don't handle.
if (PredI.definesRegister(AArch64::NZCV)) if (PredI.definesRegister(AArch64::NZCV))
return None; return None;
} }
return None; return None;
▲ Show 20 Lines • Show All 212 Lines • Show Last 20 Lines

test/CodeGen/AArch64/machine-copy-remove.mir

Show First 20 Lines • Show All 529 Lines • ▼ Show 20 Lines bb.1:
successors: %bb.2 successors: %bb.2
liveins: %x1 liveins: %x1
%x0 = MOVi64imm 4252017623040 %x0 = MOVi64imm 4252017623040
STRXui killed %x0, killed %x1, 0 STRXui killed %x0, killed %x1, 0
bb.2: bb.2:
RET_ReallyLR RET_ReallyLR
...
# Eliminate redundant MOVi32imm 4096 in bb.1 when the compare has a shifted immediate.
# CHECK-LABEL: name: test19
# CHECK: bb.1:
# CHECK-NOT: MOVi32imm
name: test19
tracksRegLiveness: true
body: |
bb.0.entry:
successors: %bb.1, %bb.2
liveins: %w0, %x1
dead %wzr = SUBSWri killed %w0, 1, 12, implicit-def %nzcv
Bcc 1, %bb.2, implicit killed %nzcv
B %bb.1
bb.1:
successors: %bb.2
liveins: %x1
%w0 = MOVi32imm 4096
STRWui killed %w0, killed %x1, 0
bb.2:
RET_ReallyLR