MachineRegionInfo: fix pass initialization

[thegameg]

Summary

• Adapt MachineBasicBlock::getName() to have the same behavior as the IR BasicBlock (Value::getName()).
• Add it to lib/CodeGen/CodeGen.cpp::initializeCodeGen so that it is linked in the CodeGen library.
• MachineRegionInfoPass's name conflicts with RegionInfoPass's name ("region").
• MachineRegionInfo should depend on MachineDominatorTree, MachinePostDominatorTree and MachineDominanceFrontier instead of their respective IR versions.
• Since there were no tests for this, add a X86 MIR test.

[arsenm]

LGTM with name fix

lib/CodeGen/MachineRegionInfo.cpp

7

machine-region-info to better match name

127

Use DEBUG_TYPE

132

Ditto

[MatzeB]

test/CodeGen/MIR/Generic/machine-region-info.ll

1–2

I'd try to write a .mir test directly, instead of only generating it as an intermediate step.

[thegameg]

• Update pass name.
• Directly add an X86 MIR test instead of generating it.

[thegameg]

• Simplify MIR test. Removing IR causes MachineBasicBlock::getName() to return "(null)".
• Return an empty string instead of "(null)" in MachineBasicBlock::getName() (same behavior as Value::getName()).

[MatzeB]

LGTM, I will commit on your behalf.

[MatzeB]

Committed in 295518

lib/CodeGen/CodeGen.cpp

void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeMachineCopyPropagationPass(Registry);
   initializeMachineDominatorTreePass(Registry);
   initializeMachineFunctionPrinterPassPass(Registry);
   initializeMachineLICMPass(Registry);
   initializeMachineLoopInfoPass(Registry);
   initializeMachineModuleInfoPass(Registry);
   initializeMachinePipelinerPass(Registry);
   initializeMachinePostDominatorTreePass(Registry);
+  initializeMachineRegionInfoPassPass(Registry);
   initializeMachineSchedulerPass(Registry);
   initializeMachineSinkingPass(Registry);
   initializeMachineVerifierPassPass(Registry);
   initializeXRayInstrumentationPass(Registry);
   initializePatchableFunctionPass(Registry);
   initializeOptimizePHIsPass(Registry);
   initializePEIPass(Registry);
   initializePHIEliminationPass(Registry);

lib/CodeGen/MachineRegionInfo.cpp

 
 #include "llvm/CodeGen/MachineRegionInfo.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/RegionInfoImpl.h"
 #include "llvm/CodeGen/MachinePostDominators.h"
 
-#define DEBUG_TYPE "region"
+#define DEBUG_TYPE "machineregions"
 
 using namespace llvm;
 
 STATISTIC(numMachineRegions,       "The # of machine regions");
 STATISTIC(numMachineSimpleRegions, "The # of simple machine regions");
 
 namespace llvm {
 template class RegionBase<RegionTraits<MachineFunction>>;

 bool MachineRegionInfoPass::runOnMachineFunction(MachineFunction &F) {
   releaseMemory();
 
   auto DT = &getAnalysis<MachineDominatorTree>();
   auto PDT = &getAnalysis<MachinePostDominatorTree>();
   auto DF = &getAnalysis<MachineDominanceFrontier>();
 
   RI.recalculate(F, DT, PDT, DF);
+
+  DEBUG(RI.dump());
+
   return false;
 }
 
 void MachineRegionInfoPass::releaseMemory() {
   RI.releaseMemory();
 }
 
 void MachineRegionInfoPass::verifyAnalysis() const {
   // Only do verification when user wants to, otherwise this expensive check
   // will be invoked by PMDataManager::verifyPreservedAnalysis when
   // a regionpass (marked PreservedAll) finish.
   if (MachineRegionInfo::VerifyRegionInfo)
     RI.verifyAnalysis();
 }
 
 void MachineRegionInfoPass::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.setPreservesAll();
-  AU.addRequiredTransitive<DominatorTreeWrapperPass>();
-  AU.addRequired<PostDominatorTreeWrapperPass>();
-  AU.addRequired<DominanceFrontierWrapperPass>();
+  AU.addRequired<MachineDominatorTree>();
+  AU.addRequired<MachinePostDominatorTree>();
+  AU.addRequired<MachineDominanceFrontier>();
+  MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 void MachineRegionInfoPass::print(raw_ostream &OS, const Module *) const {
   RI.print(OS);
 }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD void MachineRegionInfoPass::dump() const {
   RI.dump();
 }
 #endif
 
 char MachineRegionInfoPass::ID = 0;
 
-INITIALIZE_PASS_BEGIN(MachineRegionInfoPass, "regions",
+INITIALIZE_PASS_BEGIN(MachineRegionInfoPass, "machineregions",
                 "Detect single entry single exit regions", true, true)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
 INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
 INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier)
-INITIALIZE_PASS_END(MachineRegionInfoPass, "regions",
+INITIALIZE_PASS_END(MachineRegionInfoPass, "machineregions",
                 "Detect single entry single exit regions", true, true)
 
 // Create methods available outside of this file, to use them
 // "include/llvm/LinkAllPasses.h". Otherwise the pass would be deleted by
 // the link time optimization.
 
 namespace llvm {
   FunctionPass *createMachineRegionInfoPass() {
     return new MachineRegionInfoPass();
   }
 }
 

test/CodeGen/MIR/Generic/machine-region-info.ll

+; RUN: llc -stop-after virtregrewriter %s -o %t.mir
+; RUN: llc -run-pass=machineregions %t.mir -debug-only=machineregions 2>&1 | FileCheck %s
+
+define i32 @fun(i32 %a) {
+A:
+  %cmp0 = icmp eq i32 %a, 40
+  br i1 %cmp0, label %B, label %I
+
+B:
+  %cmp1 = icmp eq i32 %a, 1
+  br i1 %cmp1, label %C, label %H
+
+C:
+  %cmp2 = icmp eq i32 %a, 2
+  br i1 %cmp2, label %D, label %F
+
+D:
+  %cmp3 = icmp eq i32 %a, 90
+  br i1 %cmp3, label %E, label %F
+
+E:
+  call void @fun1(i32 100)
+  br label %F
+
+F:
+  %cmp4 = icmp eq i32 %a, 4
+  br i1 %cmp4, label %G, label %H
+
+G:
+  call void @fun1(i32 300)
+  br label %H
+
+H:
+  br label %P
+
+I:
+  %cmp5 = icmp eq i32 %a, 5
+  br i1 %cmp5, label %J, label %K
+
+J:
+  br label %L
+
+K:
+  call void @fun1(i32 400)
+  br label %L
+
+L:
+  %cmp6 = icmp eq i32 %a, 6
+  br i1 %cmp6, label %M, label %N
+
+M:
+  br label %O
+
+N:
+  call void @fun1(i32 500)
+  br label %O
+
+O:
+  br label %P
+
+P:
+  ret i32 %a
+}
+
+declare void @fun1(i32 %a)
+
+; CHECK: Region tree:
+; CHECK-NEXT: [0] A => <Function Return>
+; CHECK-NEXT:   [1] A => P
+; CHECK-NEXT:     [2] B => P
+; CHECK-NEXT:       [3] C => F
+; CHECK-NEXT:         [4] D => F
+; CHECK-NEXT:       [3] F => P
+; CHECK-NEXT:     [2] I => L
+; CHECK-NEXT:     [2] L => P
+; CHECK-NEXT: End region tree