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[X86][AVX] Remove REX_W from AVX instructions
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Authored by aymanmus on Feb 13 2017, 8:58 AM.

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craig.topper
igorb

Commits

rGb8a4f255dd63: [X86][AVX] Remove REX_W from AVX instructions.
rL295157: [X86][AVX] Remove REX_W from AVX instructions.

Summary

There is no meaning for REX_W in VEX encoded AVX instruction.

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Event Timeline

aymanmus created this revision.Feb 13 2017, 8:58 AM

LGTM

This revision is now accepted and ready to land.Feb 13 2017, 6:09 PM

Closed by commit rL295157: [X86][AVX] Remove REX_W from AVX instructions. (authored by aymanmus). · Explain WhyFeb 15 2017, 12:23 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

lib/

Target/

X86/

X86InstrSSE.td

6 lines

Diff 88207

lib/Target/X86/X86InstrSSE.td

This file is larger than 256 KB, so syntax highlighting is disabled by default.

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	/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination			/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
	multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {			multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
	def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),			def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
	(ins VR128:$src1, u8imm:$src2),			(ins VR128:$src1, u8imm:$src2),
	!strconcat(OpcodeStr,			!strconcat(OpcodeStr,
	"\t{$src2, $src1, $dst\|$dst, $src1, $src2}"),			"\t{$src2, $src1, $dst\|$dst, $src1, $src2}"),
	[(set GR64:$dst,			[(set GR64:$dst,
	(extractelt (v2i64 VR128:$src1), imm:$src2))]>,			(extractelt (v2i64 VR128:$src1), imm:$src2))]>,
	Sched<[WriteShuffle]>, REX_W;			Sched<[WriteShuffle]>;
	let SchedRW = [WriteShuffleLd, WriteRMW] in			let SchedRW = [WriteShuffleLd, WriteRMW] in
	def mr : SS4AIi8<opc, MRMDestMem, (outs),			def mr : SS4AIi8<opc, MRMDestMem, (outs),
	(ins i64mem:$dst, VR128:$src1, u8imm:$src2),			(ins i64mem:$dst, VR128:$src1, u8imm:$src2),
	!strconcat(OpcodeStr,			!strconcat(OpcodeStr,
	"\t{$src2, $src1, $dst\|$dst, $src1, $src2}"),			"\t{$src2, $src1, $dst\|$dst, $src1, $src2}"),
	[(store (extractelt (v2i64 VR128:$src1), imm:$src2),			[(store (extractelt (v2i64 VR128:$src1), imm:$src2),
	addr:$dst)]>, REX_W;			addr:$dst)]>;
	}			}

	let Predicates = [HasAVX, NoDQI] in			let Predicates = [HasAVX, NoDQI] in
	defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;			defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;

	defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;			defm PEXTRQ : SS41I_extract64<0x16, "pextrq">, REX_W;

	/// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory			/// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
	/// destination			/// destination
	multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,			multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
	OpndItins itins = DEFAULT_ITINS> {			OpndItins itins = DEFAULT_ITINS> {
	def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),			def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
	(ins VR128:$src1, u8imm:$src2),			(ins VR128:$src1, u8imm:$src2),
	!strconcat(OpcodeStr,			!strconcat(OpcodeStr,
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