[lanai] Add computeKnownBitsForTargetNode for Lanai.

[jpienaar]

Summary

computeKnownBitsForTargetNode was not defined for Lanai which resulted in additional AND's with 0x1 for the output of SETCC instructions.

[majnemer]

Hmm, this is the sort of thing I'd expect SelectionDAG to "just do"... Do other backends achieve the same end by similar means?

[majnemer]

In D29605#668334, @majnemer wrote:

Hmm, this is the sort of thing I'd expect SelectionDAG to "just do"... Do other backends achieve the same end by similar means?

I'd expect this logic to zap away such an AND: https://github.com/llvm-mirror/llvm/blob/fb21e4d6fc9ff15b231354be4068c3f732deee02/lib/CodeGen/SelectionDAG/TargetLowering.cpp#L560

[jpienaar]

Add computeKnownBitsForTargetNode for Lanai.

[jpienaar]

In D29605#668363, @majnemer wrote:

In D29605#668334, @majnemer wrote:

Hmm, this is the sort of thing I'd expect SelectionDAG to "just do"... Do other backends achieve the same end by similar means?

Yes, PPC does it in PPCTargetLowering::DAGCombineTruncBoolExt (https://github.com/llvm-mirror/llvm/blob/fb21e4d6fc9ff15b231354be4068c3f732deee02/lib/Target/PowerPC/PPCISelLowering.cpp#L9979) but in retrospect they were doing it as they have 2 different ways of setting conditional flags. For Lanai this was not needed.

I'd expect this logic to zap away such an AND: https://github.com/llvm-mirror/llvm/blob/fb21e4d6fc9ff15b231354be4068c3f732deee02/lib/CodeGen/SelectionDAG/TargetLowering.cpp#L560

This was good suggestion: it let me to seeing that computeKnownBitsForTargetNode was not defined for Lanai and so this combination would not happen. So the resulting change is much simpler and covers more cases.

[majnemer]

LGTM

lib/Target/Lanai/LanaiISelLowering.h

public:
   getSingleConstraintMatchWeight(AsmOperandInfo &Info,
                                  const char *Constraint) const override;
   void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                     std::vector<SDValue> &Ops,
                                     SelectionDAG &DAG) const override;
 
   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 
+  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
+                                     const APInt &DemandedElts,
+                                     const SelectionDAG &DAG,
+                                     unsigned Depth = 0) const override;
+
 private:
   SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
                          CallingConv::ID CallConv, bool IsVarArg,
                          bool IsTailCall,
                          const SmallVectorImpl<ISD::OutputArg> &Outs,
                          const SmallVectorImpl<SDValue> &OutVals,
                          const SmallVectorImpl<ISD::InputArg> &Ins,
                          const SDLoc &dl, SelectionDAG &DAG,

lib/Target/Lanai/LanaiISelLowering.cpp

 //===-- LanaiISelLowering.cpp - Lanai DAG Lowering Implementation ---------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the LanaiTargetLowering class.
 //
 //===----------------------------------------------------------------------===//
 
+#include "LanaiISelLowering.h"
 #include "Lanai.h"
 #include "LanaiCondCode.h"
-#include "LanaiISelLowering.h"
 #include "LanaiMachineFunctionInfo.h"
 #include "LanaiSubtarget.h"
 #include "LanaiTargetObjectFile.h"
 #include "MCTargetDesc/LanaiBaseInfo.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/CodeGen/RuntimeLibcalls.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/GlobalValue.h"
 #include "llvm/Support/Casting.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/CodeGen.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/KnownBits.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetCallingConv.h"
 #include "llvm/Target/TargetMachine.h"
 #include <cassert>
 #include <cmath>
 #include <cstdint>
 #include <cstdlib>
SDValue LanaiTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::AND:
     return combineSelectAndUseCommutative(N, DCI, /*AllOnes=*/true);
   case ISD::SUB:
     return PerformSUBCombine(N, DCI);
   }
 
   return SDValue();
 }
+
+void LanaiTargetLowering::computeKnownBitsForTargetNode(
+    const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
+    const SelectionDAG &DAG, unsigned Depth) const {
+  unsigned BitWidth = Known.getBitWidth();
+  switch (Op.getOpcode()) {
+  default:
+    break;
+  case LanaiISD::SETCC:
+    Known = KnownBits(BitWidth);
+    Known.Zero.setBits(1, BitWidth);
+    break;
+  case LanaiISD::SELECT_CC:
+    KnownBits Known2;
+    DAG.computeKnownBits(Op->getOperand(0), Known, Depth + 1);
+    DAG.computeKnownBits(Op->getOperand(1), Known2, Depth + 1);
+    Known.Zero &= Known2.Zero;
+    Known.One &= Known2.One;
+    break;
+  }
+}

lib/Target/Lanai/LanaiInstrInfo.td

 }
 
 let Uses = [SR] in {
   def SCC : InstSCC<(outs GPR:$Rs1), (ins CCOp:$DDDI),
                     "s$DDDI\t$Rs1",
                     [(set (i32 GPR:$Rs1), (LanaiSetCC imm:$DDDI))]>;
 }
 
-// SCC's output is already 1-bit so and'ing with 1 is redundant.
-def : Pat<(and (LanaiSetCC imm:$DDDI), 1), (SCC imm:$DDDI)>;
-
 // Select with hardware support
 let Uses = [SR], isSelect = 1 in {
   def SELECT : InstRR<0b111, (outs GPR:$Rd),
                       (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
                       "sel.$DDDI $Rs1, $Rs2, $Rd",
                       [(set (i32 GPR:$Rd),
                        (LanaiSelectCC (i32 GPR:$Rs1), (i32 GPR:$Rs2),
                                       (imm:$DDDI)))]> {

test/CodeGen/Lanai/masking_setccs.ll

+; RUN: llc < %s | FileCheck %s
+
+; Test that unnecessary masking with 0x1 is not inserted.
+
+target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
+target triple = "lanai"
+
+; CHECK-LABEL: masking:
+; CHECK-NOT: mov 1
+define i32 @masking(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
+entry:
+  %cmp = icmp ne i32 %a, 0
+  %cmp1 = icmp ult i32 %a, %b
+  %or.cond = and i1 %cmp, %cmp1
+  br i1 %or.cond, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %cmp2 = icmp ne i32 %b, 0
+  %cmp4 = icmp ult i32 %b, %c
+  %or.cond29 = and i1 %cmp2, %cmp4
+  br i1 %or.cond29, label %return, label %if.end6
+
+if.end6:                                          ; preds = %if.end
+  %cmp7 = icmp ne i32 %c, 0
+  %cmp9 = icmp ult i32 %c, %d
+  %or.cond30 = and i1 %cmp7, %cmp9
+  br i1 %or.cond30, label %return, label %if.end11
+
+if.end11:                                         ; preds = %if.end6
+  %cmp12 = icmp ne i32 %d, 0
+  %cmp14 = icmp ult i32 %d, %a
+  %or.cond31 = and i1 %cmp12, %cmp14
+  %b. = select i1 %or.cond31, i32 %b, i32 21
+  ret i32 %b.
+
+return:                                           ; preds = %if.end6, %if.end, %entry
+  %retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ]
+  ret i32 %retval.0
+}
+
+; CHECK-LABEL: notnot:
+; CHECK-NOT: mov 1
+define i32 @notnot(i32 %x) {
+entry:
+  %tobool = icmp ne i32 %x, 0
+  %lnot.ext = zext i1 %tobool to i32
+  ret i32 %lnot.ext
+}