[X86] Added INT1 instruction and fixed register usage.

[cray]

Summary

Documentation on INT1 can be found here:
http://www.rcollins.org/secrets/opcodes/ICEBP.html

[craig.topper]

I'd prefer not to use an undocumented instruction in codegen unless gcc or other major compiler does. Do you know if they do?

[cray]

I will work on searching through our bug reports to try and figure out what generated the undocumented instruction. We have been using this patch since llvm 3.2, so I can't remember what generated this instruction.

I don't agree with it being generated by the compiler in a normal circumstance either, but i would say that it should be available to the assembler, or an intrinsic.

[cray]

I can remove the int1 from the intrinsic. No other compiler will generate this, and it is normally generated by certain debuggers. I was able to find out that this was documented in the AMD opcode map.

I also found out that this instruction is supported by intel XED. https://github.com/intelxed/xed/blob/eb45a282de284ec2574e2b54460b37b7e587996c/datafiles/xed-isa.txt#L8238

[cray]

I just found out NASM generates this opcode for both x86 and x64. In the manual it refers to it as icebp, and says that it accepts the alias int1. I was thinking about renaming this instruction to icebp so that it is not generated by a typo in assembly. Also, the lit tests seem to match int $1 when the check line is int1

[cray]

Changed the mnemonic for INT1 to icebp, and removed it from codegen.

[craig.topper]

lib/Target/X86/X86InstrSystem.td

35

The instructions don't really modify ESP or EFLAGS. I would expect them to be restored when the interrupt handler returned. So from the perspective of the code with the INT insturction they aren't changed.

[cray]

lib/Target/X86/X86InstrSystem.td

35

The flags are pushed onto the stack, and if the INT causes an exception they will not be popped from the stack when the exception handler is called.
I can put together an example of this if you would like.

[cray]

lib/Target/X86/X86InstrSystem.td

35

I explained that poorly in my previous comment. The following is taken from the intel manual:

Flags Affected
The EFLAGS register is pushed onto the stack. The IF, TF, NT, AC, RF, and VM flags may be cleared, depending on
the mode of operation of the processor when the INT instruction is executed (see the “Operation” section). If the
interrupt uses a task gate, any flags may be set or cleared, controlled by the EFLAGS image in the new task’s TSS.

Also, in the case of windows SEH, the stack should be unwound, but the flags will not be restored.

[craig.topper]

LGTM

lib/Target/X86/X86InstrSystem.td

let mayLoad = 1, mayStore = 0, hasSideEffects = 1 in {
   def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
   def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
 }
 
 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
 
 // Interrupt and SysCall Instructions.
-let Uses = [EFLAGS] in
+let Uses = [ESP, EFLAGS], Defs = [ESP, EFLAGS] in {
   def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
+
+  def INT1 : I<0xf1, RawFrm, (outs), (ins), "int1",
+             [(int_x86_int (i8 1))], IIC_INT>;
+
   def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
-              [(int_x86_int (i8 3))], IIC_INT3>;
+
+  def INT  : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
+             [(int_x86_int imm:$trap)], IIC_INT>;
+
+}
 } // SchedRW
 
 // The long form of "int $3" turns into int3 as a size optimization.
 // FIXME: This doesn't work because InstAlias can't match immediate constants.
 //def : InstAlias<"int\t$3", (INT3)>;
 
 let SchedRW = [WriteSystem] in {
 
-def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
-              [(int_x86_int imm:$trap)], IIC_INT>;
-
-
 def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
 def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
                Requires<[In64BitMode]>;
 
 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
                  IIC_SYS_ENTER_EXIT>, TB;
 

test/CodeGen/X86/int-intrinsic.ll

 ; RUN: llc < %s -march=x86    | FileCheck %s
 ; RUN: llc < %s -march=x86-64 | FileCheck %s
 
 declare void @llvm.x86.int(i8) nounwind
 
+; CHECK: int1
+; CHECK: ret
+define void @primitive_int1 () {
+bb.entry:
+  call void @llvm.x86.int(i8 1) nounwind
+  ret void
+}
+
 ; CHECK: int3
 ; CHECK: ret
 define void @primitive_int3 () {
 bb.entry:
   call void @llvm.x86.int(i8 3) nounwind
   ret void
 }
 
 ; CHECK: int  $128
 ; CHECK: ret
 define void @primitive_int128 () {
 bb.entry:
   call void @llvm.x86.int(i8 128) nounwind
   ret void
 }

test/MC/Disassembler/X86/simple-tests.txt

 # RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 | FileCheck %s
 
 # CHECK: int  $33
 0xCD 0x21 
 
 # CHECK: int  $33
 0xCD 0x21
 
+# CHECK: int1
+0xf1
+
+# CHECK: int3
+0xcc
+
 # CHECK: jrcxz -127
 0xe3 0x81
 
 # CHECK: jecxz -127
 0x67 0xe3 0x81
 
 # CHECK: addb %al, (%rax)
 0 0

test/MC/Disassembler/X86/x86-16.txt

 0xa1 0x00 0x00
 
 # CHECK: movl 0, %eax
 0x66 0xa1 0x00 0x00
 
 # CHECK: into
 0xce
 
+# CHECK: int1
+0xf1
+
 # CHECK: int3
 0xcc
 
 # CHECK: int $4
 0xcd 0x04
 
 # CHECK: int $127
 0xcd 0x7f

test/MC/Disassembler/X86/x86-32.txt

 0xf2 0x0f 0x38 0xf0 0xc0
 
 # CHECK: crc32w %ax, %eax
 0x66 0xf2 0x0f 0x38 0xf1 0xc0
 
 # CHECK: crc32l %eax, %eax
 0xf2 0x0f 0x38 0xf1 0xc0
 
+# CHECK: int1
+0xf1
+
+# CHECK: int3
+0xcc
 
 # CHECK: int  $33
 0xCD 0x21 
 
 # CHECK: int  $33
 0xCD 0x21
 
 

test/MC/X86/x86-16.s

 movw  0, %ax
 
 // CHECK: movl 0, %eax  # encoding: [0x66,0xa1,0x00,0x00]
 movl  0, %eax
 
 into
 // CHECK: into
 // CHECK:  encoding: [0xce]
+int1
+// CHECK: int1
+// CHECK:  encoding: [0xf1]
 int3
 // CHECK: int3
 // CHECK:  encoding: [0xcc]
 int $4
 // CHECK: int $4
 // CHECK:  encoding: [0xcd,0x04]
 int $255
 // CHECK: int $255

test/MC/X86/x86-64.s

 // rdar://7986634 - Insensitivity on opcodes.
 // CHECK: int3
 INT3
 
 // rdar://8735979 - int $3 -> int3
 // CHECK: int3
 int $3
 
+// CHECK: int1
+// CHECK:  encoding: [0xf1]
+int1
+
 
 // Allow scale factor without index register.
 // CHECK: movaps  %xmm3, (%esi)
 // CHECK-STDERR: warning: scale factor without index register is ignored
 movaps %xmm3, (%esi, 2)
 
 // CHECK: imull $12, %eax
 imul $12, %eax