enable memory interleaving for X86\SLM arch.

[magabari]

Summary

originally was a part from patch: https://reviews.llvm.org/rL291657

[RKSimon]

Do you have perf stats to confirm that this is safe to do now?

lib/Target/X86/X86TargetTransformInfo.cpp

2084

I don't suppose you know what the remaining problems are with Atom are?

[mkuper]

lib/Target/X86/X86TargetTransformInfo.cpp

2084

This is my fault - I played it safe, and assumed that since SLM has problematic behavior, so does Atom, since the architectures are similar.
I wasn't aware of any Atom-specific issues when I committed this.
Of course, it's possible Intel have some new data about this, but in its absence, I'd say both are safe to remove.

[magabari]

lib/Target/X86/X86TargetTransformInfo.cpp

2084

Yes it's safe to do that now for SLM.
Regrading Atom, i didn't do any cost changes for Atom so i think this should still be disabled for Atom currently.

[RKSimon]

Did you manage to do any perf tests on SLM hardware?

[magabari]

In D28547#654982, @RKSimon wrote:

Did you manage to do any perf tests on SLM hardware?

Yes. and now it's safe to enable this feature for SLM.

[RKSimon]

OK, LGTM

lib/Target/X86/X86TargetTransformInfo.cpp

bool X86TTIImpl::areInlineCompatible(const Function *Caller,
   // correct.
   return (CallerBits & CalleeBits) == CalleeBits;
 }
 
 bool X86TTIImpl::enableInterleavedAccessVectorization() {
   // TODO: We expect this to be beneficial regardless of arch,
   // but there are currently some unexplained performance artifacts on Atom.
   // As a temporary solution, disable on Atom.
-  return !(ST->isAtom() || ST->isSLM());
+  return !(ST->isAtom());
 }
 
 // Get estimation for interleaved load/store operations and strided load.
 // \p Indices contains indices for strided load.
 // \p Factor - the factor of interleaving.
 // AVX-512 provides 3-src shuffles that significantly reduces the cost.
 int X86TTIImpl::getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy,
                                                  unsigned Factor,

test/Transforms/LoopVectorize/X86/interleaving.ll

 ; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine < %s | FileCheck %s --check-prefix=NORMAL
+; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=slm < %s | FileCheck %s --check-prefix=NORMAL
 ; RUN: opt -S -mtriple=x86_64-pc_linux -loop-vectorize -instcombine -mcpu=atom < %s | FileCheck %s --check-prefix=ATOM
 
 ; NORMAL-LABEL: foo
 ; NORMAL: %[[WIDE:.*]] = load <8 x i32>, <8 x i32>* %{{.*}}, align 4
 ; NORMAL: %[[STRIDED1:.*]] = shufflevector <8 x i32> %[[WIDE]], <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
 ; NORMAL: %[[STRIDED2:.*]] = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
 ; NORMAL: add nsw <4 x i32> %[[STRIDED2]], %[[STRIDED1]]