[AVR] Optimize 16-bit ANDs with '1'

[anmol]

Summary

Fixes PR 31345

[anmol]

Thank you, @dylanmckay

llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp

expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
 
   MI.eraseFromParent();
   return true;
 }
 
 bool AVRExpandPseudo::
   isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const {
 
+  // ANDI Rd, 0xff is redundant.
+  if (Op == AVR::ANDIRdK && ImmVal == 0xff)
+    return true;
+
   // ORI Rd, 0x0 is redundant.
   if (Op == AVR::ORIRdK && ImmVal == 0x0)
     return true;
 
   return false;
 }
 
 bool AVRExpandPseudo::

llvm/trunk/test/CodeGen/AVR/PR31345.ll

+; RUN: llc < %s -march=avr | FileCheck %s
+
+; Unit test for: PR 31345
+
+define i16 @and16_reg_imm_0xff00(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xff00
+; CHECK: andi {{r[0-9]+}}, 0
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+    %result = and i16 %a, 65280
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xffb3(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xffb3
+; CHECK: andi {{r[0-9]+}}, 179
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+    %result = and i16 %a, 65459
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0x00ff(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0x00ff
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+; CHECK: andi {{r[0-9]+}}, 0
+    %result = and i16 %a, 255
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xb3ff(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xb3ff
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+; CHECK: andi {{r[0-9]+}}, 179
+    %result = and i16 %a, 46079
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xffff(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xffff
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+; CHECK-NOT: andi {{r[0-9]+}}, 255
+    %result = and i16 %a, 65535
+    ret i16 %result
+}
+
+define i16 @and16_reg_imm_0xabcd(i16 %a) {
+; CHECK-LABEL: and16_reg_imm_0xabcd
+; CHECK: andi {{r[0-9]+}}, 205
+; CHECK: andi {{r[0-9]+}}, 171
+    %result = and i16 %a, 43981
+    ret i16 %result
+}

llvm/trunk/test/CodeGen/AVR/and.ll

 ; CHECK: and r25, r17
     %result = and i64 %a, %b
     ret i64 %result
 }
 
 define i64 @and64_reg_imm(i64 %a) {
 ; CHECK-LABEL: and64_reg_imm:
 ; CHECK: andi r18, 253
-; CHECK: andi r19, 255
+; Per PR 31345, we optimize away ANDI Rd, 0xff
+; CHECK-NOT: andi r19, 255
 ; CHECK: andi r20, 155
 ; CHECK: andi r21, 88
 ; CHECK: andi r22, 76
 ; CHECK: andi r23, 73
 ; CHECK: andi r24, 31
 ; CHECK: andi r25, 242
     %result = and i64 %a, 17446744073709551613
     ret i64 %result
 }