AMDGPU/SI: Move EXEC_LO/HI to SReg_32

[mareko]

Summary

EXEC can't be an operand of scalar stores.

[mareko]

This series fixes some issues, but in general the compiler is still in a very bad shape. There are errors like this:

• • Bad machine code: Illegal physical register for instruction ***
• function: main
• basic block: BB#0 main_body (0x8f7a98)
• instruction: S_BUFFER_STORE_DWORD_SGPR
• operand 0: %EXEC_LO

EXEC_LO is not a SReg_32_XM0 register.

It's not immediately obvious to me how to fix that.

[mareko]

Abandoned for now, but can be re-used if SGPR spilling via scalar stores ever comes back.

lib/Target/AMDGPU/SIRegisterInfo.td

 
 //===----------------------------------------------------------------------===//
 //  Register classes used as source and destination
 //===----------------------------------------------------------------------===//
 
 // Subset of SReg_32 without M0 for SMRD instructions and alike.
 // See comments in SIInstructions.td for more info.
 def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
-  (add SGPR_32, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
+  (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
    TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)> {
   let AllocationPriority = 1;
 }
 
 // Register class for all scalar registers (SGPRs + Special Registers)
 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
-  (add SReg_32_XM0, M0_CLASS)> {
+  (add SReg_32_XM0, EXEC_LO, EXEC_HI, M0_CLASS)> {
   let AllocationPriority = 1;
   let isAllocatable = 0;
 }
 
 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)> {
   let AllocationPriority = 2;
 }
 

test/CodeGen/AMDGPU/read_register.ll

 ; CHECK: buffer_store_dword [[COPY]]
 define void @test_read_flat_scratch_hi(i32 addrspace(1)* %out) #0 {
   %flat_scratch_hi = call i32 @llvm.read_register.i32(metadata !4)
   store i32 %flat_scratch_hi, i32 addrspace(1)* %out
   ret void
 }
 
 ; CHECK-LABEL: {{^}}test_read_exec_lo:
-; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_lo
+; CHECK: s_mov_b32 [[SCOPY:s[0-9]+]], exec_lo
+; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], [[SCOPY]]
 ; CHECK: buffer_store_dword [[COPY]]
 define void @test_read_exec_lo(i32 addrspace(1)* %out) #0 {
   %exec_lo = call i32 @llvm.read_register.i32(metadata !5)
   store i32 %exec_lo, i32 addrspace(1)* %out
   ret void
 }
 
 ; CHECK-LABEL: {{^}}test_read_exec_hi:
-; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_hi
+; CHECK: s_mov_b32 [[SCOPY:s[0-9]+]], exec_hi
+; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], [[SCOPY]]
 ; CHECK: buffer_store_dword [[COPY]]
 define void @test_read_exec_hi(i32 addrspace(1)* %out) #0 {
   %exec_hi = call i32 @llvm.read_register.i32(metadata !6)
   store i32 %exec_hi, i32 addrspace(1)* %out
   ret void
 }
 
 attributes #0 = { nounwind }
 
 !0 = !{!"m0"}
 !1 = !{!"exec"}
 !2 = !{!"flat_scratch"}
 !3 = !{!"flat_scratch_lo"}
 !4 = !{!"flat_scratch_hi"}
 !5 = !{!"exec_lo"}
 !6 = !{!"exec_hi"}