Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call

[dsanders]

Summary

AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output.

The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as.

All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler.

[dsanders]

Use llvm::Triple::getArch() instead of matching triples directly.

[dsanders]

Minor tweaks

[dsanders]

Here's my patch, but there's a problem with it.

As-is, it causes ~50 test failures. The ones I've looked at so far are generally due to directives such as .foo_directive or .bork_directive in inline assembly. I could go through and change each test to use valid assembly, but I think a better solution would be to have isIntegratedAsDefault() and useIntegratedAs() as the predicates and then have an equivalent to -no-integrated-as force useIntegratedAs() to return false. This is the same model as clang uses.

The effective change to the plan we previously discussed is that there is a way to force the use of EmitRawText() using -no-integrated-as. The default behaviour where targets with mature MC's always parse inline assembly remains the same.

[dsanders]

Switched to isIntegratedAsDefault() and useIntegratedAs() method.
Added -no-integrated-inline-as to llc and used it where tests required invalid
assembly, magic comments, or non-canonical output.

[• rafael]

This is certainly going on the right direction. Thank you so much for working on this!

include/llvm/MC/MCSubtargetInfo.h

48 ↗

(On Diff #6854)

Why MCSubtargeInfo? I have the impression that MCAsmInfo might be a better match. Its initialization structure is a bit more verbose, but being split among the targets matches what clang does a bit better and should allow each target to change the rules for when they use the integrated assembler without touching common code.

74 ↗

(On Diff #6854)

Don't duplicate the name on the comment.

lib/MC/MCSubtargetInfo.cpp

22 ↗

(On Diff #6854)

If going with MCasmInfo, I would suggest adding a set method to it. That way the constructor set the default and LLVMTargetMachine::initAsmInfo can call the setter if -no-integrated-inline-as is passed.

136 ↗

(On Diff #6854)

The clang logic has more cases. For example, I think the ppc assembler is used on some BSDs.
This is probably fine for now. Just change the FIXME to say that this version should be synced with clang and clang changed to use this so that we have a single implementation.

[dsanders]

Thanks for the review.

In addition to the changes suggested by comments, I'm going to drop the word 'Inline' from the variables and options. Otherwise it will be misleading when clang/llvm's logic is unified.

include/llvm/MC/MCSubtargetInfo.h

48 ↗

(On Diff #6854)

I was thinking that the maturity of MC support potentially varies on a subtarget basis. For example, if MC support for MIPS32r2 is mature, it doesn't follow that MC support for MIPS-I is also mature.

Having looked at MCAsmInfo, I agree that it's a better match and should still be able to handle any likely subtarget issues. It also has the nice benefit of keeping the targets separate in isIntegratedInlineAsDefault() since it's normally subclassed.

74 ↗

(On Diff #6854)

I did this because every other function in the file was doing the same thing. I'll remove it.

lib/MC/MCSubtargetInfo.cpp

136 ↗

(On Diff #6854)

Yes you're right. I think I've found all of them now.

[dsanders]

• Moved the predicates to MCAsmInfo.
• Implemented all (except one) of clangs conditions for whether -integrated-as is the default.
  • A couple conditions have imperfect conversions. For example testing for MachO output has become testing for Darwin.
  • getOS() == Solaris, is currently missing. There doesn't seem to be a good place to put it.
• Dropped the word 'Inline' from variables and option names. If this code is going to be unified with clang's logic then it will cover inline and non-inline asm.

[• rafael]

99% there.

Sorry for the delay with code review. The only real issue is the question about having two member variables instead of one.

include/llvm/MC/MCAsmInfo.h

309

Why do we need two variables? It seems that the constructors should be able to set UseIntegratedAssembler directly and LLVMTargetMachine.cpp can then override it if requested.

lib/MC/MCAsmInfo.cpp

96

IMHO it is the MCAsmInfoDarwin that should be named MCAsmInfoMachO. The handling of COFF and MachO are probably correct enough to not need a FIXME :-)

test/CodeGen/Generic/mature-mc-support.ll

2

nit: add something like "is parsed even when printing assembly".

[dsanders]

include/llvm/MC/MCAsmInfo.h

309

I was mostly following clang's lead for this. Clang doesn't seem to use the separation for much (the only bit I've found is that the default value is re-used as the default for -masm-verbose) so I'll change it to a single variable.

lib/MC/MCAsmInfo.cpp

96

Great. Do you have any thoughts on the 'OS is Solaris' check?

I think I can put it in SparcELFMCAsmInfo and X86ELFMCAsmInfo to cover most of it, but I'm not sure if there are other subclasses that need it.

[• rafael]

IMHO it is the MCAsmInfoDarwin that should be named MCAsmInfoMachO. The handling of COFF and MachO are probably correct enough to not need a FIXME :-)

Great. Do you have any thoughts on the 'OS is Solaris' check?

I think I can put it in SparcELFMCAsmInfo and X86ELFMCAsmInfo to cover most of it, but I'm not sure if there are other subclasses that need it.

That should do it. If people want in the future we can move it up to
MCAsmInfoELF by passing a triple down to the constructor.

Cheers,
Rafael

[dsanders]

• Removed IsIntegratedAssemblerDefault.
• Added missing 'OS is Solaris' check.
• Fixed nit.

[• rafael]

LGTM!

Thanks!

[dsanders]

Closed by commit rL201237 (authored by @dsanders).

include/llvm/MC/MCAsmInfo.h

protected:
     /// UseParensForSymbolVariant - True if target uses parens to indicate the
     /// symbol variant instead of @. For example, foo(plt) instead of foo@plt.
     bool UseParensForSymbolVariant; // Defaults to false;
 
     //===--- Prologue State ----------------------------------------------===//
 
     std::vector<MCCFIInstruction> InitialFrameState;
 
+    //===--- Integrated Assembler State ----------------------------------===//
+    /// Should we use the integrated assembler?
+    /// The integrated assembler should be enabled by default (by the
+    /// constructors) when failing to parse a valid piece of assembly (inline
+    /// or otherwise) is considered a bug. It may then be overridden after
+    /// construction (see LLVMTargetMachine::initAsmInfo()).
+    bool UseIntegratedAssembler;
+
   public:
     explicit MCAsmInfo();
     virtual ~MCAsmInfo();
 
     // FIXME: move these methods to DwarfPrinter when the JIT stops using them.
     static unsigned getSLEB128Size(int64_t Value);
     static unsigned getULEB128Size(uint64_t Value);
 
public:
 
     void addInitialFrameState(const MCCFIInstruction &Inst) {
       InitialFrameState.push_back(Inst);
     }
 
     const std::vector<MCCFIInstruction> &getInitialFrameState() const {
       return InitialFrameState;
     }
+
+    /// Return true if assembly (inline or otherwise) should be parsed.
+    bool useIntegratedAssembler() const { return UseIntegratedAssembler; }
+
+    /// Set whether assembly (inline or otherwise) should be parsed.
+    void setUseIntegratedAssembler(bool Value) {
+      UseIntegratedAssembler = Value;
+    }
   };
 }
 
 #endif

lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

void AsmPrinter::EmitInlineAsm(StringRef Str, const MDNode *LocMDNode,
                                InlineAsm::AsmDialect Dialect) const {
   assert(!Str.empty() && "Can't emit empty inline asm block");
 
   // Remember if the buffer is nul terminated or not so we can avoid a copy.
   bool isNullTerminated = Str.back() == 0;
   if (isNullTerminated)
     Str = Str.substr(0, Str.size()-1);
 
-  // If the output streamer is actually a .s file, just emit the blob textually.
+  // If the output streamer does not have mature MC support or the integrated
+  // assembler has been disabled, just emit the blob textually.
+  // Otherwise parse the asm and emit it via MC support.
   // This is useful in case the asm parser doesn't handle something but the
   // system assembler does.
-  if (OutStreamer.hasRawTextSupport()) {
+  const MCAsmInfo *MCAI = TM.getMCAsmInfo();
+  assert(MCAI && "No MCAsmInfo");
+  if (!MCAI->useIntegratedAssembler()) {
     OutStreamer.EmitRawText(Str);
     emitInlineAsmEnd(TM.getSubtarget<MCSubtargetInfo>(), 0);
     return;
   }
 
   SourceMgr SrcMgr;
   SrcMgrDiagInfo DiagInfo;
 

lib/CodeGen/LLVMTargetMachine.cpp

static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
     cl::desc("Show encoding in .s output"));
 static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
     cl::desc("Show instruction structure in .s output"));
 
 static cl::opt<cl::boolOrDefault>
 AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
            cl::init(cl::BOU_UNSET));
 
+static cl::opt<bool>
+NoIntegratedAssembler("no-integrated-as", cl::Hidden,             
+                      cl::desc("Disable integrated assembler"));
+
 static bool getVerboseAsm() {
   switch (AsmVerbose) {
   case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
   case cl::BOU_TRUE:  return true;
   case cl::BOU_FALSE: return false;
   }
   llvm_unreachable("Invalid verbose asm state");
 }
 
 void LLVMTargetMachine::initAsmInfo() {
-  AsmInfo = TheTarget.createMCAsmInfo(*getRegisterInfo(), TargetTriple);
+  MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo(*getRegisterInfo(),
+                                                    TargetTriple);
   // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
   // and if the old one gets included then MCAsmInfo will be NULL and
   // we'll crash later.
   // Provide the user with a useful error message about what's wrong.
-  assert(AsmInfo && "MCAsmInfo not initialized. "
+  assert(TmpAsmInfo && "MCAsmInfo not initialized. "
          "Make sure you include the correct TargetSelect.h"
          "and that InitializeAllTargetMCs() is being invoked!");
+
+  if (NoIntegratedAssembler)
+    TmpAsmInfo->setUseIntegratedAssembler(false);
+
+  AsmInfo = TmpAsmInfo;
 }
 
 LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
                                      StringRef CPU, StringRef FS,
                                      TargetOptions Options,
                                      Reloc::Model RM, CodeModel::Model CM,
                                      CodeGenOpt::Level OL)
   : TargetMachine(T, Triple, CPU, FS, Options) {

lib/MC/MCAsmInfo.cpp

MCAsmInfo::MCAsmInfo() {
   HasLEB128 = false;
   SupportsDebugInformation = false;
   ExceptionsType = ExceptionHandling::None;
   DwarfUsesRelocationsAcrossSections = true;
   DwarfFDESymbolsUseAbsDiff = false;
   DwarfRegNumForCFI = false;
   NeedsDwarfSectionOffsetDirective = false;
   UseParensForSymbolVariant = false;
+
+  // FIXME: Clang's logic should be synced with the logic used to initialize
+  //        this member and the two implementations should be merged.
+  // For reference:
+  // - Solaris always enables the integrated assembler by default
+  //   - SparcELFMCAsmInfo and X86ELFMCAsmInfo are handling this case
+  // - Windows always enables the integrated assembler by default
+  //   - MCAsmInfoCOFF is handling this case, should it be MCAsmInfoMicrosoft?
+  // - MachO targets always enables the integrated assembler by default
+  //   - MCAsmInfoDarwin is handling this case
+  // - Generic_GCC toolchains enable the integrated assembler on a per
+  //   architecture basis.
+  //   - The target subclasses for AArch64, ARM, and X86  handle these cases
+  UseIntegratedAssembler = false;
 }
 
 MCAsmInfo::~MCAsmInfo() {
 }
 
 
 unsigned MCAsmInfo::getULEB128Size(uint64_t Value) {
   unsigned Size = 0;

lib/MC/MCAsmInfoCOFF.cpp

MCAsmInfoCOFF::MCAsmInfoCOFF() {
   // Doesn't support visibility:
   HiddenVisibilityAttr = HiddenDeclarationVisibilityAttr = MCSA_Invalid;
   ProtectedVisibilityAttr = MCSA_Invalid;
 
   // Set up DWARF directives
   HasLEB128 = true;  // Target asm supports leb128 directives (little-endian)
   SupportsDebugInformation = true;
   NeedsDwarfSectionOffsetDirective = true;
+
+  UseIntegratedAssembler = true;
 }
 
 void MCAsmInfoMicrosoft::anchor() { }
 
 MCAsmInfoMicrosoft::MCAsmInfoMicrosoft() {
 }
 
 void MCAsmInfoGNUCOFF::anchor() { }
 
 MCAsmInfoGNUCOFF::MCAsmInfoGNUCOFF() {
 
 }

lib/MC/MCAsmInfoDarwin.cpp

MCAsmInfoDarwin::MCAsmInfoDarwin() {
 
   // Doesn't support protected visibility.
   ProtectedVisibilityAttr = MCSA_Invalid;
 
   HasDotTypeDotSizeDirective = false;
   HasNoDeadStrip = true;
 
   DwarfUsesRelocationsAcrossSections = false;
+
+  UseIntegratedAssembler = true;
 }

lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp

AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo() {
 
   UseDataRegionDirectives = true;
 
   HasLEB128 = true;
   SupportsDebugInformation = true;
 
   // Exceptions handling
   ExceptionsType = ExceptionHandling::DwarfCFI;
+
+  UseIntegratedAssembler = true;
 }
 
 // Pin the vtable to this file.
 void AArch64ELFMCAsmInfo::anchor() {}

lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp

ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin() {
   Code16Directive = ".code\t16";
   Code32Directive = ".code\t32";
   UseDataRegionDirectives = true;
 
   SupportsDebugInformation = true;
 
   // Exceptions handling
   ExceptionsType = ExceptionHandling::SjLj;
+
+  UseIntegratedAssembler = true;
 }
 
 void ARMELFMCAsmInfo::anchor() { }
 
 ARMELFMCAsmInfo::ARMELFMCAsmInfo() {
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;
 
   Data64bitsDirective = 0;
   CommentString = "@";
   Code16Directive = ".code\t16";
   Code32Directive = ".code\t32";
 
   HasLEB128 = true;
   SupportsDebugInformation = true;
 
   // Exceptions handling
   if (!DisableARMEHABI)
     ExceptionsType = ExceptionHandling::ARM;
 
   // foo(plt) instead of foo@plt
   UseParensForSymbolVariant = true;
+
+  UseIntegratedAssembler = true;
 }

lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h

class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin {
     virtual void anchor();
   public:
     explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple&);
   };
 
   class PPCLinuxMCAsmInfo : public MCAsmInfoELF {
     virtual void anchor();
   public:
-    explicit PPCLinuxMCAsmInfo(bool is64Bit);
+    explicit PPCLinuxMCAsmInfo(bool is64Bit, const Triple&);
   };
 
 } // namespace llvm
 
 #endif

lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp

PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) {
   AssemblerDialect = 1;           // New-Style mnemonics.
   SupportsDebugInformation= true; // Debug information.
 
   // The installed assembler for OSX < 10.6 lacks some directives.
   // FIXME: this should really be a check on the assembler characteristics
   // rather than OS version
   if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
     HasWeakDefCanBeHiddenDirective = false;
+
+  UseIntegratedAssembler = true;
 }
 
 void PPCLinuxMCAsmInfo::anchor() { }
 
-PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit) {
+PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit, const Triple& T) {
   if (is64Bit) {
     PointerSize = CalleeSaveStackSlotSize = 8;
   }
   IsLittleEndian = false;
 
   // ".comm align is in bytes but .align is pow-2."
   AlignmentIsInBytes = false;
 
PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit, const Triple& T) {
   MinInstAlignment = 4;
 
   // Exceptions handling
   ExceptionsType = ExceptionHandling::DwarfCFI;
     
   ZeroDirective = "\t.space\t";
   Data64bitsDirective = is64Bit ? "\t.quad\t" : 0;
   AssemblerDialect = 1;           // New-Style mnemonics.
+
+  if (T.getOS() == llvm::Triple::FreeBSD ||
+      (T.getOS() == llvm::Triple::NetBSD && !is64Bit))
+    UseIntegratedAssembler = true;
 }
 

lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp

static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
   Triple TheTriple(TT);
   bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
                   TheTriple.getArch() == Triple::ppc64le);
 
   MCAsmInfo *MAI;
   if (TheTriple.isOSDarwin())
     MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple);
   else
-    MAI = new PPCLinuxMCAsmInfo(isPPC64);
+    MAI = new PPCLinuxMCAsmInfo(isPPC64, TheTriple);
 
   // Initial state of the frame pointer is R1.
   unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1;
   MCCFIInstruction Inst =
       MCCFIInstruction::createDefCfa(0, MRI.getDwarfRegNum(Reg, true), 0);
   MAI->addInitialFrameState(Inst);
 
   return MAI;

lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp

SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) {
   CommentString = "!";
   HasLEB128 = true;
   SupportsDebugInformation = true;
 
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   SunStyleELFSectionSwitchSyntax = true;
   UsesELFSectionDirectiveForBSS = true;
+
+  if (TheTriple.getOS() == llvm::Triple::Solaris)
+    UseIntegratedAssembler = true;
 }
 
 const MCExpr*
 SparcELFMCAsmInfo::getExprForPersonalitySymbol(const MCSymbol *Sym,
                                                unsigned Encoding,
                                                MCStreamer &Streamer) const {
   if (Encoding & dwarf::DW_EH_PE_pcrel) {
     MCContext &Ctx = Streamer.getContext();

lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp

X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) {
   // rather than OS version
   if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6))
     HasWeakDefCanBeHiddenDirective = false;
 
   // FIXME: this should not depend on the target OS version, but on the ld64
   // version in use.  From at least >= ld64-97.17 (Xcode 3.2.6) the abs-ified
   // FDE relocs may be used.
   DwarfFDESymbolsUseAbsDiff = T.isMacOSX() && !T.isMacOSXVersionLT(10, 6);
+
+  UseIntegratedAssembler = true;
 }
 
 X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple)
   : X86MCAsmInfoDarwin(Triple) {
 }
 
 void X86ELFMCAsmInfo::anchor() { }
 
X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
   // Exceptions handling
   ExceptionsType = ExceptionHandling::DwarfCFI;
 
   // OpenBSD and Bitrig have buggy support for .quad in 32-bit mode, just split
   // into two .words.
   if ((T.getOS() == Triple::OpenBSD || T.getOS() == Triple::Bitrig) &&
        T.getArch() == Triple::x86)
     Data64bitsDirective = 0;
+
+  // Always enable the integrated assembler by default.
+  // Clang also enabled it when the OS is Solaris but that is redundant here.
+  UseIntegratedAssembler = true;
 }
 
 const MCExpr *
 X86_64MCAsmInfoDarwin::getExprForPersonalitySymbol(const MCSymbol *Sym,
                                                    unsigned Encoding,
                                                    MCStreamer &Streamer) const {
   MCContext &Context = Streamer.getContext();
   const MCExpr *Res =
X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) {
   if (Triple.getArch() == Triple::x86_64)
     PrivateGlobalPrefix = ".L";
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   AllowAtInName = true;
+
+  UseIntegratedAssembler = true;
 }
 
 void X86MCAsmInfoGNUCOFF::anchor() { }
 
 X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) {
   if (Triple.getArch() == Triple::x86_64)
     PrivateGlobalPrefix = ".L";
 
   AssemblerDialect = AsmWriterFlavor;
 
   TextAlignFillValue = 0x90;
 
   // Exceptions handling
   ExceptionsType = ExceptionHandling::DwarfCFI;
+
+  UseIntegratedAssembler = true;
 }

test/CodeGen/AArch64/inline-asm-constraints.ll

-;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -no-integrated-as < %s | FileCheck %s
 
 define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
 ; CHECK-LABEL: test_inline_constraint_r:
   %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset)
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
   ret i64 %val
 }
 

test/CodeGen/AArch64/inline-asm-modifiers.ll

-; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -no-integrated-as < %s | FileCheck %s
 
 @var_simple = hidden global i32 0
 @var_got = global i32 0
 @var_tlsgd = thread_local global i32 0
 @var_tlsld = thread_local(localdynamic) global i32 0
 @var_tlsie = thread_local(initialexec) global i32 0
 @var_tlsle = thread_local(localexec) global i32 0
 

test/CodeGen/ARM/2009-04-06-AsmModifier.ll

-; RUN: llc < %s -march=arm | grep "swi 107"
+; RUN: llc < %s -march=arm -no-integrated-as | grep "swi 107"
 
 define i32 @_swilseek(i32) nounwind {
 entry:
   %ptr = alloca i32   ; <i32*> [#uses=2]
   store i32 %0, i32* %ptr
   %retval = alloca i32    ; <i32*> [#uses=2]
   store i32 0, i32* %retval
   %res = alloca i32   ; <i32*> [#uses=0]

test/CodeGen/ARM/arm-modifier.ll

-; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+vfp2 -no-integrated-as | FileCheck %s
 
 define i32 @foo(float %scale, float %scale2) nounwind {
 entry:
   %scale.addr = alloca float, align 4
   %scale2.addr = alloca float, align 4
   store float %scale, float* %scale.addr, align 4
   store float %scale2, float* %scale2.addr, align 4
   %tmp = load float* %scale.addr, align 4

test/CodeGen/ARM/crash-O0.ll

-; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim
+; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim -no-integrated-as
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32"
 target triple = "armv6-apple-darwin10"
 
 %struct0 = type { i32, i32 }
 
 ; This function would crash RegAllocFast because it tried to spill %CPSR.
 define arm_apcscc void @clobber_cc() nounwind noinline ssp {
 entry:

test/CodeGen/ARM/inlineasm-64bit.ll

-; RUN: llc < %s -O3  -mtriple=arm-linux-gnueabi | FileCheck %s
-; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc < %s -O3  -mtriple=arm-linux-gnueabi -no-integrated-as | FileCheck %s
+; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs -no-integrated-as < %s | FileCheck %s
 ; check if regs are passing correctly
 define void @i64_write(i64* %p, i64 %val) nounwind {
 ; CHECK-LABEL: i64_write:
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
 ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
   %1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind
   ret void
 }

test/CodeGen/ARM/inlineasm-imm-arm.ll

-; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm -no-integrated-as
 
 ; Test ARM-mode "I" constraint, for any Data Processing immediate.
 define i32 @testI(i32 %x) {
   %y = call i32 asm "add $0, $1, $2", "=r,r,I"( i32 %x, i32 65280 ) nounwind
   ret i32 %y
 }
 
 ; Test ARM-mode "J" constraint, for compatibility with unknown use in GCC.

test/CodeGen/ARM/inlineasm3.ll

-; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 | FileCheck %s
+; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-as | FileCheck %s
 
 ; Radar 7449043
 %struct.int32x4_t = type { <4 x i32> }
 
 define void @t() nounwind {
 entry:
 ; CHECK: vmov.I64 q15, #0
 ; CHECK: vmov.32 d30[0],

test/CodeGen/ARM/mult-alt-generic-arm.ll

-; RUN: llc < %s -march=arm
+; RUN: llc < %s -march=arm -no-integrated-as
 ; ModuleID = 'mult-alt-generic.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
 target triple = "arm"
 
 @mout0 = common global i32 0, align 4
 @min1 = common global i32 0, align 4
 @marray = common global [2 x i32] zeroinitializer, align 4
 

test/CodeGen/ARM/subreg-remat.ll

-; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source | FileCheck %s
+; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-as | FileCheck %s
 target triple = "thumbv7-apple-ios"
 ; <rdar://problem/10032939>
 ;
 ; The vector %v2 is built like this:
 ;
 ;   %vreg6:ssub_1<def> = ...
 ;   %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vreg6
 ;

test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll

-; RUN: llc < %s
+; RUN: llc -no-integrated-as < %s
 ; XFAIL: sparc-sun-solaris2
 ; PR1308
 ; PR1557
 
 define i32 @stuff(i32, ...) {
         %foo = alloca i8*
         %bar = alloca i32*
         %A = call i32 asm sideeffect "inline asm $0 $2 $3 $4", "=r,0,i,m,m"( i32 0, i32 1, i8** %foo, i32** %bar )
         ret i32 %A
 }

test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll

-; RUN: llc < %s
+; RUN: llc -no-integrated-as < %s
 
 ; Test that we can have an "X" output constraint.
 
 define void @test(i16 * %t) {
         call void asm sideeffect "foo $0", "=*X,~{dirflag},~{fpsr},~{flags},~{memory}"( i16* %t )
         ret void
 }

test/CodeGen/Generic/2007-04-27-LargeMemObject.ll

-; RUN: llc < %s
+; RUN: llc -no-integrated-as < %s
 
         %struct..0anon = type { [100 x i32] }
 
 define void @test() {
 entry:
         %currfpu = alloca %struct..0anon, align 16              ; <%struct..0anon*> [#uses=2]
         %mxcsr = alloca %struct..0anon, align 16                ; <%struct..0anon*> [#uses=1]
         call void asm sideeffect "fnstenv $0", "=*m,~{dirflag},~{fpsr},~{flags}"( %struct..0anon* %currfpu )
         call void asm sideeffect "$0  $1", "=*m,*m,~{dirflag},~{fpsr},~{flags}"( %struct..0anon* %mxcsr, %struct..0anon* %currfpu )
         ret void
 }
 

test/CodeGen/Generic/2008-02-20-MatchingMem.ll

-; RUN: llc < %s
+; RUN: llc -no-integrated-as < %s
 ; PR1133
 ; XFAIL: hexagon
 define void @test(i32* %X) nounwind  {
 entry:
   %tmp1 = getelementptr i32* %X, i32 10    ; <i32*> [#uses=2]
   tail call void asm sideeffect " $0 $1 ", "=*im,*im,~{memory}"( i32* %tmp1, i32* %tmp1 ) nounwind 
   ret void
 }
 

test/CodeGen/Generic/asm-large-immediate.ll

-; RUN: llc < %s | FileCheck %s
+; RUN: llc -no-integrated-as < %s | FileCheck %s
 
 define void @test() {
 entry:
 ; CHECK: /* result: 68719476738 */
         tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 )
 ; CHECK: /* result: -68719476738 */
         tail call void asm sideeffect "/* result: ${0:n} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 )
         ret void
 }

test/CodeGen/Generic/inline-asm-mem-clobber.ll

-; RUN: llc -O2 < %s | FileCheck %s
+; RUN: llc -O2 -no-integrated-as < %s | FileCheck %s
 
 @G = common global i32 0, align 4
 
 define i32 @foo(i8* %p) nounwind uwtable {
 entry:
   %p.addr = alloca i8*, align 8
   %rv = alloca i32, align 4
   store i8* %p, i8** %p.addr, align 8

test/CodeGen/Generic/inline-asm-special-strings.ll

-; RUN: llc < %s | grep "foo 0 0"
+; RUN: llc -no-integrated-as < %s | grep "foo 0 0"
 
 define void @bar() nounwind {
   tail call void asm sideeffect "foo ${:uid} ${:uid}", ""() nounwind
   ret void
 }

test/CodeGen/Generic/mature-mc-support.ll

+; Test that inline assembly is parsed by the MC layer when MC support is mature
+; (even when the output is assembly).
+
+; RUN: not llc -march=aarch64 < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=aarch64 -filetype=obj < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=arm < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=arm -filetype=obj < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=thumb < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=thumb -filetype=obj < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=x86 < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=x86 -filetype=obj < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=x86-64 < %s 2>&1 | FileCheck %s
+; RUN: not llc -march=x86-64 -filetype=obj < %s 2>&1 | FileCheck %s
+
+module asm " .this_directive_is_very_unlikely_to_exist"
+
+; CHECK: LLVM ERROR: Error parsing inline asm

test/CodeGen/PowerPC/2007-04-24-InlineAsm-I-Modifier.ll

-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep "foo r3, r4"
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 | grep "bari r3, 47"
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 -no-integrated-as | grep "foo r3, r4"
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8.8.0 -no-integrated-as | grep "bari r3, 47"
 
 ; PR1351
 
 define i32 @test1(i32 %Y, i32 %X) nounwind {
   %tmp1 = tail call i32 asm "foo${1:I} $0, $1", "=r,rI"( i32 %X )
   ret i32 %tmp1
 }
 
 define i32 @test2(i32 %Y, i32 %X) nounwind {
   %tmp1 = tail call i32 asm "bar${1:I} $0, $1", "=r,rI"( i32 47 )
   ret i32 %tmp1
 }

test/CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll

-; RUN: llc < %s
+; RUN: llc -no-integrated-as < %s
 ; PR1382
 
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "powerpc-apple-darwin8.8.0"
 @x = global [2 x i32] [ i32 1, i32 2 ]    ; <[2 x i32]*> [#uses=1]
 
 define void @foo() {
 entry:
   tail call void asm sideeffect "$0 $1", "s,i"( i8* bitcast (i32* getelementptr ([2 x i32]* @x, i32 0, i32 1) to i8*), i8* bitcast (i32* getelementptr ([2 x i32]* @x, i32 0, i32 1) to i8*) )
   ret void
 }

test/CodeGen/Thumb/inlineasm-imm-thumb.ll

-; RUN: llc < %s -march=thumb
+; RUN: llc < %s -march=thumb -no-integrated-as
 
 ; Test Thumb-mode "I" constraint, for ADD immediate.
 define i32 @testI(i32 %x) {
   %y = call i32 asm "add $0, $1, $2", "=r,r,I"( i32 %x, i32 255 ) nounwind
   ret i32 %y
 }
 
 ; Test Thumb-mode "J" constraint, for negated ADD immediates.

test/CodeGen/X86/2006-07-20-InlineAsm.ll

-; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86 -no-integrated-as
 ; PR833
 
 @G = weak global i32 0    ; <i32*> [#uses=3]
 
 define i32 @foo(i32 %X) {
 entry:
   %X_addr = alloca i32    ; <i32*> [#uses=3]
   store i32 %X, i32* %X_addr

test/CodeGen/X86/2006-07-31-SingleRegClass.ll

 ; PR850
-; RUN: llc < %s -march=x86 -x86-asm-syntax=att | FileCheck %s
+; RUN: llc < %s -march=x86 -x86-asm-syntax=att -no-integrated-as | FileCheck %s
 
 ; CHECK: {{movl 4[(]%eax[)],%ebp}}
 ; CHECK: {{movl 0[(]%eax[)], %ebx}}
 
 define i32 @foo(i32 %__s.i.i, i32 %tmp5.i.i, i32 %tmp6.i.i, i32 %tmp7.i.i, i32 %tmp8.i.i) {
   %tmp9.i.i = call i32 asm sideeffect "push %ebp\0Apush %ebx\0Amovl 4($2),%ebp\0Amovl 0($2), %ebx\0Amovl $1,%eax\0Aint  $$0x80\0Apop  %ebx\0Apop %ebp", "={ax},i,0,{cx},{dx},{si},{di}"( i32 192, i32 %__s.i.i, i32 %tmp5.i.i, i32 %tmp6.i.i, i32 %tmp7.i.i, i32 %tmp8.i.i )    ; <i32> [#uses=1]
   ret i32 %tmp9.i.i
 }
 

test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll

-; RUN: llc < %s -march=x86 | grep "mov %gs:72, %eax"
+; RUN: llc < %s -march=x86 -no-integrated-as | grep "mov %gs:72, %eax"
 target datalayout = "e-p:32:32"
 target triple = "i686-apple-darwin9"
 
 define void @test() {
   %tmp1 = tail call i32* asm sideeffect "mov %gs:${1:P}, $0", "=r,i,~{dirflag},~{fpsr},~{flags}"( i32 72 )    ; <%struct._pthread*> [#uses=1]
   ret void
 }
 
 

test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

-; RUN: llc < %s -mcpu=yonah -march=x86 | FileCheck %s
+; RUN: llc < %s -mcpu=yonah -march=x86 -no-integrated-as | FileCheck %s
 
 target datalayout = "e-p:32:32"
 target triple = "i686-apple-darwin9"
 
 ; CHECK: {{cmpltsd %xmm0, %xmm0}}
 
 define void @acoshf() {
   %tmp19 = tail call <2 x double> asm sideeffect "pcmpeqd $0, $0 \0A\09 cmpltsd $0, $0", "=x,0,~{dirflag},~{fpsr},~{flags}"( <2 x double> zeroinitializer )    ; <<2 x double>> [#uses=0]
   ret void
 }
 

test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll

-; RUN: llc < %s
+; RUN: llc -no-integrated-as < %s
 ; PR1748
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @kernel_init(i8* %unused) {
 entry:
   call void asm sideeffect "foo ${0:q}", "=*imr"( i64* null )
   ret i32 0
 }
 

test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll

-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu
+; RUN: llc -no-integrated-as < %s -mtriple=x86_64-unknown-linux-gnu
 ; PR1767
 
 define void @xor_sse_2(i64 %bytes, i64* %p1, i64* %p2) {
 entry:
         %p2_addr = alloca i64*          ; <i64**> [#uses=2]
         %lines = alloca i32             ; <i32*> [#uses=2]
         store i64* %p2, i64** %p2_addr, align 8
         %tmp1 = lshr i64 %bytes, 8              ; <i64> [#uses=1]
         %tmp12 = trunc i64 %tmp1 to i32         ; <i32> [#uses=2]
         store i32 %tmp12, i32* %lines, align 4
         %tmp6 = call i64* asm sideeffect "foo",
 "=r,=*r,=*r,r,0,1,2,~{dirflag},~{fpsr},~{flags},~{memory}"( i64** %p2_addr,
 i32* %lines, i64 256, i64* %p1, i64* %p2, i32 %tmp12 )              ; <i64*> [#uses=0]
         ret void
 }

test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll

-; RUN: llc < %s -relocation-model=static | FileCheck %s
+; RUN: llc < %s -relocation-model=static -no-integrated-as | FileCheck %s
 ; PR1761
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-pc-linux"
 @str = internal constant [12 x i8] c"init/main.c\00"    ; <[12 x i8]*> [#uses=1]
 
 ; CHECK: {{foo str$}}
 
 define i32 @unknown_bootoption() {
 entry:
   tail call void asm sideeffect "foo ${0:c}\0A", "i,~{dirflag},~{fpsr},~{flags}"( i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) )
   ret i32 undef
 }

test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll

-; RUN: llc < %s | FileCheck %s
+; RUN: llc -no-integrated-as < %s | FileCheck %s
 ; PR2078
 ; The clobber list says that "ax" is clobbered.  Make sure that eax isn't 
 ; allocated to the input/output register.
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin8"
 @pixels = weak global i32 0   ; <i32*> [#uses=2]
 
 define void @test() nounwind  {

test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll

-; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86 -no-integrated-as
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
 target triple = "i386-pc-linux-gnu"
 
 define void @dct_unquantize_h263_intra_mmx(i16* %block, i32 %n, i32 %qscale) nounwind  {
 entry:
   %tmp1 = shl i32 %qscale, 1    ; <i32> [#uses=1]
   br i1 false, label %bb46, label %bb59
 
 bb46:   ; preds = %entry
   ret void
 
 bb59:   ; preds = %entry
   tail call void asm sideeffect "movd $1, %mm6                 \0A\09packssdw %mm6, %mm6          \0A\09packssdw %mm6, %mm6          \0A\09movd $2, %mm5                 \0A\09pxor %mm7, %mm7              \0A\09packssdw %mm5, %mm5          \0A\09packssdw %mm5, %mm5          \0A\09psubw %mm5, %mm7             \0A\09pxor %mm4, %mm4              \0A\09.align 1<<4\0A\091:                             \0A\09movq ($0, $3), %mm0           \0A\09movq 8($0, $3), %mm1          \0A\09pmullw %mm6, %mm0            \0A\09pmullw %mm6, %mm1            \0A\09movq ($0, $3), %mm2           \0A\09movq 8($0, $3), %mm3          \0A\09pcmpgtw %mm4, %mm2           \0A\09pcmpgtw %mm4, %mm3           \0A\09pxor %mm2, %mm0              \0A\09pxor %mm3, %mm1              \0A\09paddw %mm7, %mm0             \0A\09paddw %mm7, %mm1             \0A\09pxor %mm0, %mm2              \0A\09pxor %mm1, %mm3              \0A\09pcmpeqw %mm7, %mm0           \0A\09pcmpeqw %mm7, %mm1           \0A\09pandn %mm2, %mm0             \0A\09pandn %mm3, %mm1             \0A\09movq %mm0, ($0, $3)           \0A\09movq %mm1, 8($0, $3)          \0A\09add $$16, $3                    \0A\09jng 1b                         \0A\09", "r,imr,imr,r,~{dirflag},~{fpsr},~{flags},~{memory}"( i16* null, i32 %tmp1, i32 0, i32 0 ) nounwind 
   ret void
 }

test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll

-; RUN: llc < %s | FileCheck %s
+; RUN: llc -no-integrated-as < %s | FileCheck %s
 ; rdar://5720231
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin8"
 
 define void @test() nounwind  {
 ; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: 1 $2 3
 ; CHECK: ret
 
   tail call void asm sideeffect " ${0:c} $1 ${2:c} ", "imr,imr,i,~{dirflag},~{fpsr},~{flags}"( i32 1, i32 2, i32 3 ) nounwind 
   ret void
 }
 

test/CodeGen/X86/2008-09-18-inline-asm-2.ll

-; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 | FileCheck %s
-; RUN: llc < %s -march=x86 -regalloc=basic      | FileCheck %s
-; RUN: llc < %s -march=x86 -regalloc=greedy     | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 -no-integrated-as | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=basic -no-integrated-as      | FileCheck %s
+; RUN: llc < %s -march=x86 -regalloc=greedy -no-integrated-as     | FileCheck %s
 
 ; The 1st, 2nd, 3rd and 5th registers must all be different.  The registers
 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
 ; operand.
 ;
 ; CHECK: 1st=[[A1:%...]]
 ; CHECK-NOT: [[A1]]
 ; CHECK: 2nd=[[A2:%...]]

test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll

-; RUN: llc < %s -march=x86
-; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86 -no-integrated-as
+; RUN: llc < %s -march=x86-64 -no-integrated-as
 
 define void @test(i64 %x) nounwind {
 entry:
   tail call void asm sideeffect "ASM: $0", "r,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
   ret void
 }
 

test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll

-; RUN: llc < %s -march=x86
-; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86 -no-integrated-as
+; RUN: llc < %s -march=x86-64 -no-integrated-as
 
 ; from gcc.c-torture/compile/920520-1.c
 
 define i32 @g() nounwind {
 entry:
   call void asm sideeffect "$0", "r"(double 1.500000e+00) nounwind
   ret i32 0
 }
 

test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll

-; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc < %s -march=x86 -no-integrated-as | FileCheck %s
 
 ; ModuleID = 'shant.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin9.6"
 
 define void @f() nounwind {
 ; CHECK-LABEL: f:
 ; CHECK-NOT: ret

test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll

-; RUN: llc < %s -mtriple=i386-apple-darwin
+; RUN: llc < %s -mtriple=i386-apple-darwin -no-integrated-as
 ; rdar://6781755
 ; PR3934
 
   %0 = type { i32, i32 }    ; type %0
 
 define void @bn_sqr_comba8(i32* nocapture %r, i32* %a) nounwind {
 entry:
   %asmtmp23 = tail call %0 asm "mulq $3", "={ax},={dx},{ax},*m,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32* %a) nounwind    ; <%0> [#uses=1]
   %asmresult25 = extractvalue %0 %asmtmp23, 1    ; <i32> [#uses=1]
   %asmtmp26 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={dx},=r,imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 %asmresult25, i32 0) nounwind    ; <%0> [#uses=1]
   %asmresult27 = extractvalue %0 %asmtmp26, 0    ; <i32> [#uses=1]
   %asmtmp29 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={ax},={dx},imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 0, i32 %asmresult27) nounwind    ; <%0> [#uses=0]
   ret void
 }

test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll

-; RUN: llc < %s -relocation-model=static | FileCheck %s
+; RUN: llc < %s -relocation-model=static -no-integrated-as | FileCheck %s
 ; PR4152
 
 ; CHECK: {{1: ._pv_cpu_ops[+]8}}
 ; CHECK: {{2: ._G}}
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin9.6"
   %struct.pv_cpu_ops = type { i32, [2 x i32] }

test/CodeGen/X86/2009-09-19-earlyclobber.ll

-; RUN: llc < %s | FileCheck %s
+; RUN: llc -no-integrated-as < %s | FileCheck %s
 ; ModuleID = '4964.c'
 ; PR 4964
 ; Registers other than RAX, RCX are OK, but they must be different.
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin10.0"
   %0 = type { i64, i64 }    ; type %0
 
 define i64 @flsst(i64 %find) nounwind ssp {
 entry:
 ; CHECK: FOO %rax %rcx
   %asmtmp = tail call %0 asm sideeffect "FOO $0 $1 $2", "=r,=&r,rm,~{dirflag},~{fpsr},~{flags},~{cc}"(i64 %find) nounwind    ; <%0> [#uses=1]
   %asmresult = extractvalue %0 %asmtmp, 0    ; <i64> [#uses=1]
   ret i64 %asmresult
 }

test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll

-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-as | FileCheck %s
 ; pr5391
 
 define void @t() nounwind ssp {
 entry:
 ; CHECK-LABEL: t:
 ; CHECK: movl %ecx, %eax
 ; CHECK: %eax = foo (%eax, %ecx)
   %b = alloca i32                                 ; <i32*> [#uses=2]

test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll

-; RUN: llc < %s -O0 -regalloc=fast | FileCheck %s
+; RUN: llc < %s -O0 -regalloc=fast -no-integrated-as | FileCheck %s
 ; PR6520
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
 target triple = "i386-apple-darwin10.0.0"
 
 %0 = type { i8*, i8*, i32 }
 
 define i8* @func() nounwind ssp {

test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll

-; RUN: llc -regalloc=fast -optimize-regalloc=0 < %s | FileCheck %s
+; RUN: llc -regalloc=fast -optimize-regalloc=0 -no-integrated-as < %s | FileCheck %s
 ; PR7382
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"
 
 @.str = private constant [23 x i8] c"This should be -1: %d\0A\00" ; <[23 x i8]*> [#uses=1]
 
 define i32 @main() {
 entry:

test/CodeGen/X86/2010-06-25-asm-RA-crash.ll

-; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32
+; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32 -no-integrated-as
 
 %struct.__SEH2Frame = type {}
 
 define void @_SEH2FrameHandler() nounwind {
 entry:
   %target.addr.i = alloca i8*, align 4            ; <i8**> [#uses=2]
   %frame = alloca %struct.__SEH2Frame*, align 4   ; <%struct.__SEH2Frame**> [#uses=1]
   %tmp = load %struct.__SEH2Frame** %frame        ; <%struct.__SEH2Frame*> [#uses=1]

test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll

-; RUN: llc < %s -march=x86 -O0 | FileCheck %s
+; RUN: llc < %s -march=x86 -O0 -no-integrated-as | FileCheck %s
 ; PR7509
 target triple = "i386-apple-darwin10"
 %asmtype = type { i32, i8*, i32, i32 }
 
 ; Arguments 1 and 4 must be the same. No other output arguments may be
 ; allocated %eax.
 
 ; CHECK: InlineAsm Start

test/CodeGen/X86/2010-06-28-matched-g-constraint.ll

-; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -no-integrated-as | FileCheck %s
 ; Any register is OK for %0, but it must be a register, not memory.
 
 define i32 @foo() nounwind ssp {
 entry:
 ; CHECK: GCROOT %eax
   %_r = alloca i32, align 4                       ; <i32*> [#uses=2]
   call void asm "/* GCROOT $0 */", "=*imr,0,~{dirflag},~{fpsr},~{flags}"(i32* %_r, i32 4) nounwind
   %0 = load i32* %_r, align 4                     ; <i32> [#uses=1]
   ret i32 %0
 }

test/CodeGen/X86/2010-07-02-asm-alignstack.ll

-; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -no-integrated-as | FileCheck %s
 
 define void @foo() nounwind ssp {
 entry:
 ; CHECK: foo
 ; CHECK: pushq
 ; CHECK: int $3
   call void asm sideeffect alignstack "# top of block", "~{dirflag},~{fpsr},~{flags},~{edi},~{esi},~{edx},~{ecx},~{eax}"() nounwind
   call void asm sideeffect alignstack ".file \22small.c\22", "~{dirflag},~{fpsr},~{flags}"() nounwind

test/CodeGen/X86/2010-07-06-asm-RIP.ll

-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-as | FileCheck %s
 ; PR 4752
 
 @n = global i32 0                                 ; <i32*> [#uses=2]
 
 define void @f(i32*) nounwind ssp {
   ret void
 }
 

test/CodeGen/X86/2010-07-13-indirectXconstraint.ll

-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-as | FileCheck %s
 ; PR 7528
 ; formerly crashed
 
 %0 = type { [12 x i16] }
 %union..0anon = type { [3 x <1 x i64>] }
 
 @gsm_H.1466 = internal constant %0 { [12 x i16] [i16 -134, i16 -374, i16 0, i16 2054, i16 5741, i16 8192, i16 5741, i16 2054, i16 0, i16 -374, i16 -134, i16 0] }, align 8 ; <%0*> [#uses=1]
 

test/CodeGen/X86/2011-10-11-SpillDead.ll

-; RUN: llc < %s -verify-regalloc
+; RUN: llc < %s -verify-regalloc -no-integrated-as
 ; PR11125
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.7"
 
 ; The inline asm takes %x as a GR32_ABCD virtual register.
 ; The call to @g forces a spill of that register.
 ;
 ; The asm has a dead output tied to %x.

test/CodeGen/X86/asm-block-labels.ll

-; RUN: opt < %s -std-compile-opts | llc
+; RUN: opt < %s -std-compile-opts | llc -no-integrated-as
 ; ModuleID = 'block12.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i686-apple-darwin8"
 
 define void @bar() {
 entry:
   br label %"LASM$foo"
 

test/CodeGen/X86/asm-global-imm.ll

-; RUN: llc < %s -march=x86 -relocation-model=static | FileCheck %s
+; RUN: llc < %s -march=x86 -relocation-model=static -no-integrated-as | FileCheck %s
 ; PR882
 
 target datalayout = "e-p:32:32"
 target triple = "i686-apple-darwin9.0.0d2"
 @GV = weak global i32 0   ; <i32*> [#uses=2]
 @str = external global [12 x i8]    ; <[12 x i8]*> [#uses=1]
 
 define void @foo() {

test/CodeGen/X86/cas.ll

-; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - | FileCheck %s
+; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - -no-integrated-as | FileCheck %s
 
 ; C code this came from
 ;bool cas(float volatile *p, float *expected, float desired) {
 ;  bool success;
 ;  __asm__ __volatile__("lock; cmpxchg %[desired], %[mem]; "
 ;                       "mov %[expected], %[expected_out]; "
 ;                       "sete %[success]"
 ;                       : [success] "=a" (success),

test/CodeGen/X86/fast-isel.ll

-; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2
-; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10
+; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2 -no-integrated-as
+; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10 -no-integrated-as
 
 ; This tests very minimal fast-isel functionality.
 
 define i32* @foo(i32* %p, i32* %q, i32** %z) nounwind {
 entry:
   %r = load i32* %p
   %s = load i32* %q
   %y = load i32** %z

test/CodeGen/X86/fold-xmm-zero.ll

-; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 -no-integrated-as | FileCheck %s
 
 ; Simple test to make sure folding for special constants (like float zero)
 ; isn't completely broken.
 
 ; CHECK: divss  LCPI0
 
 %0 = type { float, float, float, float, float, float, float, float }
 

test/CodeGen/X86/inline-asm-flag-clobber.ll

-; RUN: llc -march=x86-64 < %s | FileCheck %s
+; RUN: llc -march=x86-64 -no-integrated-as < %s | FileCheck %s
 ; PR3701
 
 define i64 @t(i64* %arg) nounwind {
         br i1 true, label %1, label %5
 
 ; <label>:1             ; preds = %0
         %2 = icmp eq i64* null, %arg            ; <i1> [#uses=1]
         %3 = tail call i64* asm sideeffect "movl %fs:0,$0", "=r,~{dirflag},~{fpsr},~{flags}"() nounwind         ; <%struct.thread*> [#uses=0]

test/CodeGen/X86/inline-asm-fpstack.ll

-; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin | FileCheck %s
+; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin -no-integrated-as | FileCheck %s
 
 ; There should be no stack manipulations between the inline asm and ret.
 ; CHECK: test1
 ; CHECK: InlineAsm End
 ; CHECK-NEXT: ret
 define x86_fp80 @test1() {
         %tmp85 = call x86_fp80 asm sideeffect "fld0", "={st(0)}"()
         ret x86_fp80 %tmp85

test/CodeGen/X86/inline-asm-h.ll

 ; RUN: llc -mtriple=x86_64-pc-linux-gnu < %s | FileCheck %s
 
 @foobar = common global i32 0, align 4
 
 define void @zed() nounwind {
 entry:
   call void asm "movq %mm2,${0:H}", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* @foobar) nounwind
   ret void
 }
 
 ; CHECK: zed
-; CHECK: movq %mm2,foobar+8(%rip)
+; CHECK: movq %mm2, foobar+8(%rip)

test/CodeGen/X86/inline-asm-modifier-n.ll

-; RUN: llc < %s -march=x86 | grep " 37"
+; RUN: llc < %s -march=x86 -no-integrated-as | grep " 37"
 ; rdar://7008959
 
 define void @bork() nounwind {
 entry:
   tail call void asm sideeffect "BORK ${0:n}", "i,~{dirflag},~{fpsr},~{flags}"(i32 -37) nounwind
   ret void
 }

test/CodeGen/X86/inline-asm-mrv.ll

 ; PR2094
-; RUN: llc < %s -march=x86-64 | grep movslq
-; RUN: llc < %s -march=x86-64 | grep addps
-; RUN: llc < %s -march=x86-64 | grep paddd
-; RUN: llc < %s -march=x86-64 | not grep movq
+; RUN: llc < %s -march=x86-64 -no-integrated-as | grep movslq
+; RUN: llc < %s -march=x86-64 -no-integrated-as | grep addps
+; RUN: llc < %s -march=x86-64 -no-integrated-as | grep paddd
+; RUN: llc < %s -march=x86-64 -no-integrated-as | not grep movq
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin8"
 
 define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind  {
   %tmp12 = sext i32 %stride to i64    ; <i64> [#uses=1]
   %mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6",
          "=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind

test/CodeGen/X86/inline-asm-q-regs.ll

-; RUN: llc < %s -march=x86-64 -mattr=+avx
+; RUN: llc < %s -march=x86-64 -mattr=+avx -no-integrated-as
 ; rdar://7066579
 
   %0 = type { i64, i64, i64, i64, i64 }    ; type %0
 
 define void @test1() nounwind {
 entry:
   %asmtmp = call %0 asm sideeffect "mov    %cr0, $0       \0Amov    %cr2, $1       \0Amov    %cr3, $2       \0Amov    %cr4, $3       \0Amov    %cr8, $0       \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind    ; <%0> [#uses=0]
   ret void

test/CodeGen/X86/inline-asm-stack-realign3.ll

-; RUN: llc -march=x86 < %s | FileCheck %s
+; RUN: llc -march=x86 -no-integrated-as < %s | FileCheck %s
 
 declare void @bar(i32* %junk)
 
 define i32 @foo(i1 %cond) {
 entry:
   %r = alloca i32, align 128
   store i32 -1, i32* %r, align 128
   br i1 %cond, label %doit, label %skip

test/CodeGen/X86/inline-asm-tied.ll

-; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic -no-integrated-as | FileCheck %s
 ; rdar://6992609
 
 ; CHECK: movl [[EDX:%e..]], 4(%esp)
 ; CHECK: movl [[EDX]], 4(%esp)
 target triple = "i386-apple-darwin9.0"
 @llvm.used = appending global [1 x i8*] [i8* bitcast (i64 (i64)* @_OSSwapInt64 to i8*)], section "llvm.metadata"    ; <[1 x i8*]*> [#uses=0]
 
 define i64 @_OSSwapInt64(i64 %_data) nounwind {

test/CodeGen/X86/inline-asm-x-scalar.ll

-; RUN: llc < %s -march=x86 -mcpu=yonah
+; RUN: llc < %s -march=x86 -mcpu=yonah -no-integrated-as
 
 define void @test1() {
         tail call void asm sideeffect "ucomiss $0", "x"( float 0x41E0000000000000)
         ret void
 }
 
 define void @test2() {
         %tmp53 = tail call i32 asm "ucomiss $1, $3\0Acmovae  $2, $0 ", "=r,mx,mr,x,0,~{dirflag},~{fpsr},~{flags},~{cc}"( float 0x41E0000000000000, i32 2147483647, float 0.000000e+00, i32 0 )         ; <i32> [#uses

test/CodeGen/X86/inline-asm.ll

-; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86 -no-integrated-as
 
 define i32 @test1() nounwind {
   ; Dest is AX, dest type = i32.
         %tmp4 = call i32 asm sideeffect "FROB $0", "={ax}"()
         ret i32 %tmp4
 }
 
 define void @test2(i32 %V) nounwind {

test/CodeGen/X86/ms-inline-asm.ll

-; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=core2 -no-integrated-as | FileCheck %s
 
 define i32 @t1() nounwind {
 entry:
   %0 = tail call i32 asm sideeffect inteldialect "mov eax, $1\0A\09mov $0, eax", "=r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
   ret i32 %0
 ; CHECK: t1
 ; CHECK: {{## InlineAsm Start|#APP}}
 ; CHECK: .intel_syntax

test/CodeGen/X86/mult-alt-generic-i686.ll

-; RUN: llc < %s -march=x86
+; RUN: llc < %s -march=x86 -no-integrated-as
 ; ModuleID = 'mult-alt-generic.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
 target triple = "i686"
 
 @mout0 = common global i32 0, align 4
 @min1 = common global i32 0, align 4
 @marray = common global [2 x i32] zeroinitializer, align 4
 

test/CodeGen/X86/mult-alt-generic-x86_64.ll

-; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86-64 -no-integrated-as
 ; ModuleID = 'mult-alt-generic.c'
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64"
 
 @mout0 = common global i32 0, align 4
 @min1 = common global i32 0, align 4
 @marray = common global [2 x i32] zeroinitializer, align 4
 

test/CodeGen/X86/mult-alt-x86.ll

-; RUN: llc < %s -march=x86 -mattr=+sse2
+; RUN: llc < %s -march=x86 -mattr=+sse2 -no-integrated-as
 ; ModuleID = 'mult-alt-x86.c'
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
 target triple = "i686-pc-win32"
 
 @mout0 = common global i32 0, align 4
 @min1 = common global i32 0, align 4
 @dout0 = common global double 0.000000e+000, align 8
 @din1 = common global double 0.000000e+000, align 8

test/CodeGen/X86/multiple-loop-post-inc.ll

-; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem < %s | FileCheck %s
+; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem -no-integrated-as < %s | FileCheck %s
 ; rdar://7236213
 ;
 ; The scheduler's 2-address hack has been disabled, so there is
 ; currently no good guarantee that this test will pass until the
 ; machine scheduler develops an equivalent heuristic.
 
 ; CodeGen shouldn't require any lea instructions inside the marked loop.
 ; It should properly set up post-increment uses and do coalescing for

test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll

-; RUN: opt < %s -std-compile-opts -o - | llc -o - | grep bork_directive | wc -l | grep 2
+; RUN: opt < %s -std-compile-opts -o - | llc -no-integrated-as -o - | grep bork_directive | wc -l | grep 2
 
 ;; We don't want branch folding to fold asm directives.
 
 define void @bork(i32 %param) {
 entry:
   %tmp = icmp eq i32 %param, 0
         br i1 %tmp, label %cond_true, label %cond_false