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Differential D2686

Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call
ClosedPublic

Authored by dsanders on Feb 4 2014, 5:48 AM.

Details

Reviewers
• rafael
Commits
rL201333: Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove…
rL201237: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove…
Summary

AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output.

The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as.

All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler.

Diff Detail

Event Timeline

dsanders updated this revision to Unknown Object (????).Feb 4 2014, 6:12 AM

Use llvm::Triple::getArch() instead of matching triples directly.

dsanders updated this revision to Unknown Object (????).Feb 4 2014, 6:27 AM

Minor tweaks

dsanders added a subscriber: Unknown Object (MLST).Feb 4 2014, 6:28 AM
dsanders added a reviewer: • rafael.Feb 4 2014, 6:39 AM

Here's my patch, but there's a problem with it.

As-is, it causes ~50 test failures. The ones I've looked at so far are generally due to directives such as .foo_directive or .bork_directive in inline assembly. I could go through and change each test to use valid assembly, but I think a better solution would be to have isIntegratedAsDefault() and useIntegratedAs() as the predicates and then have an equivalent to -no-integrated-as force useIntegratedAs() to return false. This is the same model as clang uses.

The effective change to the plan we previously discussed is that there is a way to force the use of EmitRawText() using -no-integrated-as. The default behaviour where targets with mature MC's always parse inline assembly remains the same.

dsanders updated this revision to Unknown Object (????).Feb 4 2014, 9:06 AM

Switched to isIntegratedAsDefault() and useIntegratedAs() method.
Added -no-integrated-inline-as to llc and used it where tests required invalid
assembly, magic comments, or non-canonical output.

• rafael added a comment.Feb 4 2014, 9:44 AM

This is certainly going on the right direction. Thank you so much for working on this!

include/llvm/MC/MCSubtargetInfo.h
48

Why MCSubtargeInfo? I have the impression that MCAsmInfo might be a better match. Its initialization structure is a bit more verbose, but being split among the targets matches what clang does a bit better and should allow each target to change the rules for when they use the integrated assembler without touching common code.

74

Don't duplicate the name on the comment.

lib/MC/MCSubtargetInfo.cpp
22

If going with MCasmInfo, I would suggest adding a set method to it. That way the constructor set the default and LLVMTargetMachine::initAsmInfo can call the setter if -no-integrated-inline-as is passed.

136

The clang logic has more cases. For example, I think the ppc assembler is used on some BSDs.
This is probably fine for now. Just change the FIXME to say that this version should be synced with clang and clang changed to use this so that we have a single implementation.

dsanders added a comment.Feb 5 2014, 7:39 AM

Thanks for the review.

In addition to the changes suggested by comments, I'm going to drop the word 'Inline' from the variables and options. Otherwise it will be misleading when clang/llvm's logic is unified.

include/llvm/MC/MCSubtargetInfo.h
48

I was thinking that the maturity of MC support potentially varies on a subtarget basis. For example, if MC support for MIPS32r2 is mature, it doesn't follow that MC support for MIPS-I is also mature.

Having looked at MCAsmInfo, I agree that it's a better match and should still be able to handle any likely subtarget issues. It also has the nice benefit of keeping the targets separate in isIntegratedInlineAsDefault() since it's normally subclassed.

74

I did this because every other function in the file was doing the same thing. I'll remove it.

lib/MC/MCSubtargetInfo.cpp
136

Yes you're right. I think I've found all of them now.

dsanders updated this revision to Unknown Object (????).Feb 6 2014, 2:54 AM
  • Moved the predicates to MCAsmInfo.
  • Implemented all (except one) of clangs conditions for whether -integrated-as is the default.
    • A couple conditions have imperfect conversions. For example testing for MachO output has become testing for Darwin.
    • getOS() == Solaris, is currently missing. There doesn't seem to be a good place to put it.
  • Dropped the word 'Inline' from variables and option names. If this code is going to be unified with clang's logic then it will cover inline and non-inline asm.
• rafael added a comment.Feb 9 2014, 8:02 PM

99% there.

Sorry for the delay with code review. The only real issue is the question about having two member variables instead of one.

include/llvm/MC/MCAsmInfo.h
309 ↗(On Diff #6917)

Why do we need two variables? It seems that the constructors should be able to set UseIntegratedAssembler directly and LLVMTargetMachine.cpp can then override it if requested.

lib/MC/MCAsmInfo.cpp
96 ↗(On Diff #6917)

IMHO it is the MCAsmInfoDarwin that should be named MCAsmInfoMachO. The handling of COFF and MachO are probably correct enough to not need a FIXME :-)

test/CodeGen/Generic/mature-mc-support.ll
2

nit: add something like "is parsed even when printing assembly".

dsanders added inline comments.Feb 10 2014, 9:41 AM
include/llvm/MC/MCAsmInfo.h
309 ↗(On Diff #6917)

I was mostly following clang's lead for this. Clang doesn't seem to use the separation for much (the only bit I've found is that the default value is re-used as the default for -masm-verbose) so I'll change it to a single variable.

lib/MC/MCAsmInfo.cpp
96 ↗(On Diff #6917)

Great. Do you have any thoughts on the 'OS is Solaris' check?

I think I can put it in SparcELFMCAsmInfo and X86ELFMCAsmInfo to cover most of it, but I'm not sure if there are other subclasses that need it.

• rafael added a comment.Feb 10 2014, 11:17 AM

IMHO it is the MCAsmInfoDarwin that should be named MCAsmInfoMachO. The handling of COFF and MachO are probably correct enough to not need a FIXME :-)

Great. Do you have any thoughts on the 'OS is Solaris' check?

I think I can put it in SparcELFMCAsmInfo and X86ELFMCAsmInfo to cover most of it, but I'm not sure if there are other subclasses that need it.

That should do it. If people want in the future we can move it up to
MCAsmInfoELF by passing a triple down to the constructor.

Cheers,
Rafael

dsanders updated this revision to Unknown Object (????).Feb 11 2014, 7:13 AM
  • Removed IsIntegratedAssemblerDefault.
  • Added missing 'OS is Solaris' check.
  • Fixed nit.
• rafael accepted this revision.Feb 11 2014, 11:32 AM

LGTM!

Thanks!

dsanders closed this revision.Feb 12 2014, 6:51 AM
dsanders closed this revision.

Closed by commit rL201237 (authored by @dsanders).

eush mentioned this in D53938: [MC] Implement EmitRawText in MCNullStreamer.Oct 31 2018, 9:40 AM
dsanders mentioned this in rL345841: [MC] Implement EmitRawText in MCNullStreamer.Nov 1 2018, 8:43 AM

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Diff 6854

include/llvm/MC/MCSubtargetInfo.h

Show All 39 Linesclass MCSubtargetInfo {
const InstrStage *Stages; // Instruction itinerary stages const InstrStage *Stages; // Instruction itinerary stages
const unsigned *OperandCycles; // Itinerary operand cycles const unsigned *OperandCycles; // Itinerary operand cycles
const unsigned *ForwardingPaths; // Forwarding paths const unsigned *ForwardingPaths; // Forwarding paths
unsigned NumFeatures; // Number of processor features unsigned NumFeatures; // Number of processor features
unsigned NumProcs; // Number of processors unsigned NumProcs; // Number of processors
uint64_t FeatureBits; // Feature bits for current CPU + FS uint64_t FeatureBits; // Feature bits for current CPU + FS
bool UseIntegratedInlineAs; // Should we use the integrated assembler for
rafaelUnsubmitted
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Why MCSubtargeInfo? I have the impression that MCAsmInfo might be a better match. Its initialization structure is a bit more verbose, but being split among the targets matches what clang does a bit better and should allow each target to change the rules for when they use the integrated assembler without touching common code.

rafael: Why MCSubtargeInfo? I have the impression that MCAsmInfo might be a better match. Its…
dsandersAuthorUnsubmitted
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I was thinking that the maturity of MC support potentially varies on a subtarget basis. For example, if MC support for MIPS32r2 is mature, it doesn't follow that MC support for MIPS-I is also mature.

Having looked at MCAsmInfo, I agree that it's a better match and should still be able to handle any likely subtarget issues. It also has the nice benefit of keeping the targets separate in isIntegratedInlineAsDefault() since it's normally subclassed.

dsanders: I was thinking that the maturity of MC support potentially varies on a subtarget basis. For…
// inline assembly on this subtarget.
public: public:
void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
const SubtargetFeatureKV *PF, const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD, const SubtargetFeatureKV *PD,
const SubtargetInfoKV *ProcSched, const SubtargetInfoKV *ProcSched,
const MCWriteProcResEntry *WPR, const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL, const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const MCReadAdvanceEntry *RA,
const InstrStage *IS, const InstrStage *IS,
const unsigned *OC, const unsigned *FP, const unsigned *OC, const unsigned *FP,
unsigned NF, unsigned NP); unsigned NF, unsigned NP);
/// getTargetTriple - Return the target triple string. /// getTargetTriple - Return the target triple string.
StringRef getTargetTriple() const { StringRef getTargetTriple() const {
return TargetTriple; return TargetTriple;
} }
/// getFeatureBits - Return the feature bits. /// getFeatureBits - Return the feature bits.
/// ///
uint64_t getFeatureBits() const { uint64_t getFeatureBits() const {
return FeatureBits; return FeatureBits;
} }
/// useIntegratedInlineAs - Return true if the inline assembly should be
rafaelUnsubmitted
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Don't duplicate the name on the comment.

rafael: Don't duplicate the name on the comment.
dsandersAuthorUnsubmitted
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I did this because every other function in the file was doing the same thing. I'll remove it.

dsanders: I did this because every other function in the file was doing the same thing. I'll remove it.
/// parsed.
bool useIntegratedInlineAs() const { return UseIntegratedInlineAs; }
/// isIntegratedAsDefault - Is the integrated assembler enabled by default
/// The integrated assembler should be enabled by default when failing to
/// parse a valid piece of assembly (inline or otherwise) is considered a bug.
bool isIntegratedAsDefault(StringRef TT) const;
/// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
/// feature string). Recompute feature bits and scheduling model. /// feature string). Recompute feature bits and scheduling model.
void InitMCProcessorInfo(StringRef CPU, StringRef FS); void InitMCProcessorInfo(StringRef CPU, StringRef FS);
/// InitCPUSchedModel - Recompute scheduling model based on CPU. /// InitCPUSchedModel - Recompute scheduling model based on CPU.
void InitCPUSchedModel(StringRef CPU); void InitCPUSchedModel(StringRef CPU);
/// ToggleFeature - Toggle a feature and returns the re-computed feature /// ToggleFeature - Toggle a feature and returns the re-computed feature
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Linesvoid AsmPrinter::EmitInlineAsm(StringRef Str, const MDNode *LocMDNode,
InlineAsm::AsmDialect Dialect) const { InlineAsm::AsmDialect Dialect) const {
assert(!Str.empty() && "Can't emit empty inline asm block"); assert(!Str.empty() && "Can't emit empty inline asm block");
// Remember if the buffer is nul terminated or not so we can avoid a copy. // Remember if the buffer is nul terminated or not so we can avoid a copy.
bool isNullTerminated = Str.back() == 0; bool isNullTerminated = Str.back() == 0;
if (isNullTerminated) if (isNullTerminated)
Str = Str.substr(0, Str.size()-1); Str = Str.substr(0, Str.size()-1);
// If the output streamer is actually a .s file, just emit the blob textually. // If the output streamer does not have mature MC support or the integrated
// assembler has been disabled, just emit the blob textually.
// Otherwise parse the asm and emit it via MC support.
// This is useful in case the asm parser doesn't handle something but the // This is useful in case the asm parser doesn't handle something but the
// system assembler does. // system assembler does.
if (OutStreamer.hasRawTextSupport()) { if (!TM.getSubtarget<MCSubtargetInfo>().useIntegratedInlineAs()) {
OutStreamer.EmitRawText(Str); OutStreamer.EmitRawText(Str);
emitInlineAsmEnd(TM.getSubtarget<MCSubtargetInfo>(), 0); emitInlineAsmEnd(TM.getSubtarget<MCSubtargetInfo>(), 0);
return; return;
} }
SourceMgr SrcMgr; SourceMgr SrcMgr;
SrcMgrDiagInfo DiagInfo; SrcMgrDiagInfo DiagInfo;
▲ Show 20 Lines • Show All 460 Lines • Show Last 20 Lines

lib/MC/MCSubtargetInfo.cpp

//===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===// //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Triple.h" #include "llvm/ADT/Triple.h"
#include "llvm/MC/MCInstrItineraries.h" #include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/SubtargetFeature.h" #include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
#include "llvm/Support/CommandLine.h"
#include <algorithm> #include <algorithm>
using namespace llvm; using namespace llvm;
static cl::opt<bool>
NoIntegratedInlineAs("no-integrated-inline-as", cl::Hidden,
rafaelUnsubmitted
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If going with MCasmInfo, I would suggest adding a set method to it. That way the constructor set the default and LLVMTargetMachine::initAsmInfo can call the setter if -no-integrated-inline-as is passed.

rafael: If going with MCasmInfo, I would suggest adding a set method to it. That way the constructor…
cl::desc("Disable integrated assembly of inline asm"));
MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors. MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
/// InitMCProcessorInfo - Set or change the CPU (optionally supplemented /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented
/// with feature string). Recompute feature bits and scheduling model. /// with feature string). Recompute feature bits and scheduling model.
void void
MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) { MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
SubtargetFeatures Features(FS); SubtargetFeatures Features(FS);
FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
Show All 31 LinesMCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
ReadAdvanceTable = RA; ReadAdvanceTable = RA;
Stages = IS; Stages = IS;
OperandCycles = OC; OperandCycles = OC;
ForwardingPaths = FP; ForwardingPaths = FP;
NumFeatures = NF; NumFeatures = NF;
NumProcs = NP; NumProcs = NP;
UseIntegratedInlineAs = isIntegratedAsDefault(TT);
if (NoIntegratedInlineAs)
UseIntegratedInlineAs = false;
InitMCProcessorInfo(CPU, FS); InitMCProcessorInfo(CPU, FS);
} }
/// ToggleFeature - Toggle a feature and returns the re-computed feature /// ToggleFeature - Toggle a feature and returns the re-computed feature
/// bits. This version does not change the implied bits. /// bits. This version does not change the implied bits.
uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) { uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
FeatureBits ^= FB; FeatureBits ^= FB;
return FeatureBits; return FeatureBits;
Show All 39 LinesMCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths); return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
} }
/// Initialize an InstrItineraryData instance. /// Initialize an InstrItineraryData instance.
void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const { void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
InstrItins = InstrItins =
InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths); InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);
} }
bool MCSubtargetInfo::isIntegratedAsDefault(StringRef TT) const {
Triple Trip(TT);
// This should be kept in sync with clang
if (Trip.getArch() == llvm::Triple::aarch64 ||
rafaelUnsubmitted
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The clang logic has more cases. For example, I think the ppc assembler is used on some BSDs.
This is probably fine for now. Just change the FIXME to say that this version should be synced with clang and clang changed to use this so that we have a single implementation.

rafael: The clang logic has more cases. For example, I think the ppc assembler is used on some BSDs.
dsandersAuthorUnsubmitted
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Yes you're right. I think I've found all of them now.

dsanders: Yes you're right. I think I've found all of them now.
Trip.getArch() == llvm::Triple::arm ||
Trip.getArch() == llvm::Triple::x86 ||
Trip.getArch() == llvm::Triple::x86_64 ||
Trip.getArch() == llvm::Triple::thumb)
return true;
return false;
}

test/CodeGen/AArch64/inline-asm-constraints.ll

;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s ;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -no-integrated-inline-as < %s | FileCheck %s
define i64 @test_inline_constraint_r(i64 %base, i32 %offset) { define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
; CHECK-LABEL: test_inline_constraint_r: ; CHECK-LABEL: test_inline_constraint_r:
%val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset) %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset)
; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
ret i64 %val ret i64 %val
} }
▲ Show 20 Lines • Show All 128 Lines • Show Last 20 Lines

test/CodeGen/AArch64/inline-asm-modifiers.ll

; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -no-integrated-inline-as < %s | FileCheck %s
@var_simple = hidden global i32 0 @var_simple = hidden global i32 0
@var_got = global i32 0 @var_got = global i32 0
@var_tlsgd = thread_local global i32 0 @var_tlsgd = thread_local global i32 0
@var_tlsld = thread_local(localdynamic) global i32 0 @var_tlsld = thread_local(localdynamic) global i32 0
@var_tlsie = thread_local(initialexec) global i32 0 @var_tlsie = thread_local(initialexec) global i32 0
@var_tlsle = thread_local(localexec) global i32 0 @var_tlsle = thread_local(localexec) global i32 0
▲ Show 20 Lines • Show All 138 Lines • Show Last 20 Lines

test/CodeGen/ARM/2009-04-06-AsmModifier.ll

; RUN: llc < %s -march=arm | grep "swi 107" ; RUN: llc < %s -march=arm -no-integrated-inline-as | grep "swi 107"
define i32 @_swilseek(i32) nounwind { define i32 @_swilseek(i32) nounwind {
entry: entry:
%ptr = alloca i32 ; <i32*> [#uses=2] %ptr = alloca i32 ; <i32*> [#uses=2]
store i32 %0, i32* %ptr store i32 %0, i32* %ptr
%retval = alloca i32 ; <i32*> [#uses=2] %retval = alloca i32 ; <i32*> [#uses=2]
store i32 0, i32* %retval store i32 0, i32* %retval
%res = alloca i32 ; <i32*> [#uses=0] %res = alloca i32 ; <i32*> [#uses=0]
Show All 11 Lines

test/CodeGen/ARM/arm-modifier.ll

; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s ; RUN: llc < %s -march=arm -mattr=+vfp2 -no-integrated-inline-as | FileCheck %s
define i32 @foo(float %scale, float %scale2) nounwind { define i32 @foo(float %scale, float %scale2) nounwind {
entry: entry:
%scale.addr = alloca float, align 4 %scale.addr = alloca float, align 4
%scale2.addr = alloca float, align 4 %scale2.addr = alloca float, align 4
store float %scale, float* %scale.addr, align 4 store float %scale, float* %scale.addr, align 4
store float %scale2, float* %scale2.addr, align 4 store float %scale2, float* %scale2.addr, align 4
%tmp = load float* %scale.addr, align 4 %tmp = load float* %scale.addr, align 4
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

test/CodeGen/ARM/crash-O0.ll

; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim ; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim -no-integrated-inline-as
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "armv6-apple-darwin10" target triple = "armv6-apple-darwin10"
%struct0 = type { i32, i32 } %struct0 = type { i32, i32 }
; This function would crash RegAllocFast because it tried to spill %CPSR. ; This function would crash RegAllocFast because it tried to spill %CPSR.
define arm_apcscc void @clobber_cc() nounwind noinline ssp { define arm_apcscc void @clobber_cc() nounwind noinline ssp {
entry: entry:
Show All 19 Lines

test/CodeGen/ARM/inlineasm-64bit.ll

; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi | FileCheck %s ; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi -no-integrated-inline-as | FileCheck %s
; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs -no-integrated-inline-as < %s | FileCheck %s
; check if regs are passing correctly ; check if regs are passing correctly
define void @i64_write(i64* %p, i64 %val) nounwind { define void @i64_write(i64* %p, i64 %val) nounwind {
; CHECK-LABEL: i64_write: ; CHECK-LABEL: i64_write:
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}] ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
%1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind %1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind
ret void ret void
} }
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test/CodeGen/ARM/inlineasm-imm-arm.ll

; RUN: llc < %s -march=arm ; RUN: llc < %s -march=arm -no-integrated-inline-as
; Test ARM-mode "I" constraint, for any Data Processing immediate. ; Test ARM-mode "I" constraint, for any Data Processing immediate.
define i32 @testI(i32 %x) { define i32 @testI(i32 %x) {
%y = call i32 asm "add $0, $1, $2", "=r,r,I"( i32 %x, i32 65280 ) nounwind %y = call i32 asm "add $0, $1, $2", "=r,r,I"( i32 %x, i32 65280 ) nounwind
ret i32 %y ret i32 %y
} }
; Test ARM-mode "J" constraint, for compatibility with unknown use in GCC. ; Test ARM-mode "J" constraint, for compatibility with unknown use in GCC.
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test/CodeGen/ARM/inlineasm3.ll

; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 | FileCheck %s ; RUN: llc < %s -march=arm -float-abi=soft -mattr=+neon,+v6t2 -no-integrated-inline-as | FileCheck %s
; Radar 7449043 ; Radar 7449043
%struct.int32x4_t = type { <4 x i32> } %struct.int32x4_t = type { <4 x i32> }
define void @t() nounwind { define void @t() nounwind {
entry: entry:
; CHECK: vmov.I64 q15, #0 ; CHECK: vmov.I64 q15, #0
; CHECK: vmov.32 d30[0], ; CHECK: vmov.32 d30[0],
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test/CodeGen/ARM/mult-alt-generic-arm.ll

; RUN: llc < %s -march=arm ; RUN: llc < %s -march=arm -no-integrated-inline-as
; ModuleID = 'mult-alt-generic.c' ; ModuleID = 'mult-alt-generic.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"
target triple = "arm" target triple = "arm"
@mout0 = common global i32 0, align 4 @mout0 = common global i32 0, align 4
@min1 = common global i32 0, align 4 @min1 = common global i32 0, align 4
@marray = common global [2 x i32] zeroinitializer, align 4 @marray = common global [2 x i32] zeroinitializer, align 4
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test/CodeGen/ARM/subreg-remat.ll

; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source | FileCheck %s ; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -pre-RA-sched=source -no-integrated-inline-as | FileCheck %s
target triple = "thumbv7-apple-ios" target triple = "thumbv7-apple-ios"
; <rdar://problem/10032939> ; <rdar://problem/10032939>
; ;
; The vector %v2 is built like this: ; The vector %v2 is built like this:
; ;
; %vreg6:ssub_1<def> = ... ; %vreg6:ssub_1<def> = ...
; %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vreg6 ; %vreg6:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg; mem:LD4[ConstantPool] DPR_VFP2:%vreg6
; ;
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test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll

; RUN: llc < %s ; RUN: llc -no-integrated-inline-as < %s
; XFAIL: sparc-sun-solaris2 ; XFAIL: sparc-sun-solaris2
; PR1308 ; PR1308
; PR1557 ; PR1557
define i32 @stuff(i32, ...) { define i32 @stuff(i32, ...) {
%foo = alloca i8* %foo = alloca i8*
%bar = alloca i32* %bar = alloca i32*
%A = call i32 asm sideeffect "inline asm $0 $2 $3 $4", "=r,0,i,m,m"( i32 0, i32 1, i8** %foo, i32** %bar ) %A = call i32 asm sideeffect "inline asm $0 $2 $3 $4", "=r,0,i,m,m"( i32 0, i32 1, i8** %foo, i32** %bar )
ret i32 %A ret i32 %A
} }

test/CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll

; RUN: llc < %s ; RUN: llc -no-integrated-inline-as < %s
; Test that we can have an "X" output constraint. ; Test that we can have an "X" output constraint.
define void @test(i16 * %t) { define void @test(i16 * %t) {
call void asm sideeffect "foo $0", "=*X,~{dirflag},~{fpsr},~{flags},~{memory}"( i16* %t ) call void asm sideeffect "foo $0", "=*X,~{dirflag},~{fpsr},~{flags},~{memory}"( i16* %t )
ret void ret void
} }

test/CodeGen/Generic/2007-04-27-LargeMemObject.ll

; RUN: llc < %s ; RUN: llc -no-integrated-inline-as < %s
%struct..0anon = type { [100 x i32] } %struct..0anon = type { [100 x i32] }
define void @test() { define void @test() {
entry: entry:
%currfpu = alloca %struct..0anon, align 16 ; <%struct..0anon*> [#uses=2] %currfpu = alloca %struct..0anon, align 16 ; <%struct..0anon*> [#uses=2]
%mxcsr = alloca %struct..0anon, align 16 ; <%struct..0anon*> [#uses=1] %mxcsr = alloca %struct..0anon, align 16 ; <%struct..0anon*> [#uses=1]
call void asm sideeffect "fnstenv $0", "=*m,~{dirflag},~{fpsr},~{flags}"( %struct..0anon* %currfpu ) call void asm sideeffect "fnstenv $0", "=*m,~{dirflag},~{fpsr},~{flags}"( %struct..0anon* %currfpu )
call void asm sideeffect "$0 $1", "=*m,*m,~{dirflag},~{fpsr},~{flags}"( %struct..0anon* %mxcsr, %struct..0anon* %currfpu ) call void asm sideeffect "$0 $1", "=*m,*m,~{dirflag},~{fpsr},~{flags}"( %struct..0anon* %mxcsr, %struct..0anon* %currfpu )
ret void ret void
} }

test/CodeGen/Generic/2008-02-20-MatchingMem.ll

; RUN: llc < %s ; RUN: llc -no-integrated-inline-as < %s
; PR1133 ; PR1133
; XFAIL: hexagon ; XFAIL: hexagon
define void @test(i32* %X) nounwind { define void @test(i32* %X) nounwind {
entry: entry:
%tmp1 = getelementptr i32* %X, i32 10 ; <i32*> [#uses=2] %tmp1 = getelementptr i32* %X, i32 10 ; <i32*> [#uses=2]
tail call void asm sideeffect " $0 $1 ", "=*im,*im,~{memory}"( i32* %tmp1, i32* %tmp1 ) nounwind tail call void asm sideeffect " $0 $1 ", "=*im,*im,~{memory}"( i32* %tmp1, i32* %tmp1 ) nounwind
ret void ret void
} }

test/CodeGen/Generic/asm-large-immediate.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc -no-integrated-inline-as < %s | FileCheck %s
define void @test() { define void @test() {
entry: entry:
; CHECK: /* result: 68719476738 */ ; CHECK: /* result: 68719476738 */
tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 ) tail call void asm sideeffect "/* result: ${0:c} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 )
; CHECK: /* result: -68719476738 */ ; CHECK: /* result: -68719476738 */
tail call void asm sideeffect "/* result: ${0:n} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 ) tail call void asm sideeffect "/* result: ${0:n} */", "i,~{dirflag},~{fpsr},~{flags}"( i64 68719476738 )
ret void ret void
} }

test/CodeGen/Generic/inline-asm-mem-clobber.ll

; RUN: llc -O2 < %s | FileCheck %s ; RUN: llc -O2 -no-integrated-inline-as < %s | FileCheck %s
@G = common global i32 0, align 4 @G = common global i32 0, align 4
define i32 @foo(i8* %p) nounwind uwtable { define i32 @foo(i8* %p) nounwind uwtable {
entry: entry:
%p.addr = alloca i8*, align 8 %p.addr = alloca i8*, align 8
%rv = alloca i32, align 4 %rv = alloca i32, align 4
store i8* %p, i8** %p.addr, align 8 store i8* %p, i8** %p.addr, align 8
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test/CodeGen/Generic/inline-asm-special-strings.ll

; RUN: llc < %s | grep "foo 0 0" ; RUN: llc -no-integrated-inline-as < %s | grep "foo 0 0"
define void @bar() nounwind { define void @bar() nounwind {
tail call void asm sideeffect "foo ${:uid} ${:uid}", ""() nounwind tail call void asm sideeffect "foo ${:uid} ${:uid}", ""() nounwind
ret void ret void
} }

test/CodeGen/Generic/mature-mc-support.ll

  • This file was added.
; Test that inline assembly is parsed by the MC layer when MC support is mature.
rafaelUnsubmitted
Not Done
ReplyInline Actions

nit: add something like "is parsed even when printing assembly".

rafael: nit: add something like "is parsed even when printing assembly".
; RUN: not llc -march=aarch64 < %s 2>&1 | FileCheck %s
; RUN: not llc -march=aarch64 -filetype=obj < %s 2>&1 | FileCheck %s
; RUN: not llc -march=arm < %s 2>&1 | FileCheck %s
; RUN: not llc -march=arm -filetype=obj < %s 2>&1 | FileCheck %s
; RUN: not llc -march=thumb < %s 2>&1 | FileCheck %s
; RUN: not llc -march=thumb -filetype=obj < %s 2>&1 | FileCheck %s
; RUN: not llc -march=x86 < %s 2>&1 | FileCheck %s
; RUN: not llc -march=x86 -filetype=obj < %s 2>&1 | FileCheck %s
; RUN: not llc -march=x86-64 < %s 2>&1 | FileCheck %s
; RUN: not llc -march=x86-64 -filetype=obj < %s 2>&1 | FileCheck %s
module asm " .this_directive_is_very_unlikely_to_exist"
; CHECK: LLVM ERROR: Error parsing inline asm

test/CodeGen/Thumb/inlineasm-imm-thumb.ll

; RUN: llc < %s -march=thumb ; RUN: llc < %s -march=thumb -no-integrated-inline-as
; Test Thumb-mode "I" constraint, for ADD immediate. ; Test Thumb-mode "I" constraint, for ADD immediate.
define i32 @testI(i32 %x) { define i32 @testI(i32 %x) {
%y = call i32 asm "add $0, $1, $2", "=r,r,I"( i32 %x, i32 255 ) nounwind %y = call i32 asm "add $0, $1, $2", "=r,r,I"( i32 %x, i32 255 ) nounwind
ret i32 %y ret i32 %y
} }
; Test Thumb-mode "J" constraint, for negated ADD immediates. ; Test Thumb-mode "J" constraint, for negated ADD immediates.
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test/CodeGen/X86/2006-07-20-InlineAsm.ll

; RUN: llc < %s -march=x86 ; RUN: llc < %s -march=x86 -no-integrated-inline-as
; PR833 ; PR833
@G = weak global i32 0 ; <i32*> [#uses=3] @G = weak global i32 0 ; <i32*> [#uses=3]
define i32 @foo(i32 %X) { define i32 @foo(i32 %X) {
entry: entry:
%X_addr = alloca i32 ; <i32*> [#uses=3] %X_addr = alloca i32 ; <i32*> [#uses=3]
store i32 %X, i32* %X_addr store i32 %X, i32* %X_addr
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test/CodeGen/X86/2006-07-31-SingleRegClass.ll

; PR850 ; PR850
; RUN: llc < %s -march=x86 -x86-asm-syntax=att | FileCheck %s ; RUN: llc < %s -march=x86 -x86-asm-syntax=att -no-integrated-inline-as | FileCheck %s
; CHECK: {{movl 4[(]%eax[)],%ebp}} ; CHECK: {{movl 4[(]%eax[)],%ebp}}
; CHECK: {{movl 0[(]%eax[)], %ebx}} ; CHECK: {{movl 0[(]%eax[)], %ebx}}
define i32 @foo(i32 %__s.i.i, i32 %tmp5.i.i, i32 %tmp6.i.i, i32 %tmp7.i.i, i32 %tmp8.i.i) { define i32 @foo(i32 %__s.i.i, i32 %tmp5.i.i, i32 %tmp6.i.i, i32 %tmp7.i.i, i32 %tmp8.i.i) {
%tmp9.i.i = call i32 asm sideeffect "push %ebp\0Apush %ebx\0Amovl 4($2),%ebp\0Amovl 0($2), %ebx\0Amovl $1,%eax\0Aint $$0x80\0Apop %ebx\0Apop %ebp", "={ax},i,0,{cx},{dx},{si},{di}"( i32 192, i32 %__s.i.i, i32 %tmp5.i.i, i32 %tmp6.i.i, i32 %tmp7.i.i, i32 %tmp8.i.i ) ; <i32> [#uses=1] %tmp9.i.i = call i32 asm sideeffect "push %ebp\0Apush %ebx\0Amovl 4($2),%ebp\0Amovl 0($2), %ebx\0Amovl $1,%eax\0Aint $$0x80\0Apop %ebx\0Apop %ebp", "={ax},i,0,{cx},{dx},{si},{di}"( i32 192, i32 %__s.i.i, i32 %tmp5.i.i, i32 %tmp6.i.i, i32 %tmp7.i.i, i32 %tmp8.i.i ) ; <i32> [#uses=1]
ret i32 %tmp9.i.i ret i32 %tmp9.i.i
} }

test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll

; RUN: llc < %s -march=x86 | grep "mov %gs:72, %eax" ; RUN: llc < %s -march=x86 -no-integrated-inline-as | grep "mov %gs:72, %eax"
target datalayout = "e-p:32:32" target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin9" target triple = "i686-apple-darwin9"
define void @test() { define void @test() {
%tmp1 = tail call i32* asm sideeffect "mov %gs:${1:P}, $0", "=r,i,~{dirflag},~{fpsr},~{flags}"( i32 72 ) ; <%struct._pthread*> [#uses=1] %tmp1 = tail call i32* asm sideeffect "mov %gs:${1:P}, $0", "=r,i,~{dirflag},~{fpsr},~{flags}"( i32 72 ) ; <%struct._pthread*> [#uses=1]
ret void ret void
} }

test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

; RUN: llc < %s -mcpu=yonah -march=x86 | FileCheck %s ; RUN: llc < %s -mcpu=yonah -march=x86 -no-integrated-inline-as | FileCheck %s
target datalayout = "e-p:32:32" target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin9" target triple = "i686-apple-darwin9"
; CHECK: {{cmpltsd %xmm0, %xmm0}} ; CHECK: {{cmpltsd %xmm0, %xmm0}}
define void @acoshf() { define void @acoshf() {
%tmp19 = tail call <2 x double> asm sideeffect "pcmpeqd $0, $0 \0A\09 cmpltsd $0, $0", "=x,0,~{dirflag},~{fpsr},~{flags}"( <2 x double> zeroinitializer ) ; <<2 x double>> [#uses=0] %tmp19 = tail call <2 x double> asm sideeffect "pcmpeqd $0, $0 \0A\09 cmpltsd $0, $0", "=x,0,~{dirflag},~{fpsr},~{flags}"( <2 x double> zeroinitializer ) ; <<2 x double>> [#uses=0]
ret void ret void
} }

test/CodeGen/X86/2007-10-28-inlineasm-q-modifier.ll

; RUN: llc < %s ; RUN: llc -no-integrated-inline-as < %s
; PR1748 ; PR1748
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define i32 @kernel_init(i8* %unused) { define i32 @kernel_init(i8* %unused) {
entry: entry:
call void asm sideeffect "foo ${0:q}", "=*imr"( i64* null ) call void asm sideeffect "foo ${0:q}", "=*imr"( i64* null )
ret i32 0 ret i32 0
} }

test/CodeGen/X86/2007-11-04-LiveVariablesBug.ll

; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu ; RUN: llc -no-integrated-inline-as < %s -mtriple=x86_64-unknown-linux-gnu
; PR1767 ; PR1767
define void @xor_sse_2(i64 %bytes, i64* %p1, i64* %p2) { define void @xor_sse_2(i64 %bytes, i64* %p1, i64* %p2) {
entry: entry:
%p2_addr = alloca i64* ; <i64**> [#uses=2] %p2_addr = alloca i64* ; <i64**> [#uses=2]
%lines = alloca i32 ; <i32*> [#uses=2] %lines = alloca i32 ; <i32*> [#uses=2]
store i64* %p2, i64** %p2_addr, align 8 store i64* %p2, i64** %p2_addr, align 8
%tmp1 = lshr i64 %bytes, 8 ; <i64> [#uses=1] %tmp1 = lshr i64 %bytes, 8 ; <i64> [#uses=1]
%tmp12 = trunc i64 %tmp1 to i32 ; <i32> [#uses=2] %tmp12 = trunc i64 %tmp1 to i32 ; <i32> [#uses=2]
store i32 %tmp12, i32* %lines, align 4 store i32 %tmp12, i32* %lines, align 4
%tmp6 = call i64* asm sideeffect "foo", %tmp6 = call i64* asm sideeffect "foo",
"=r,=*r,=*r,r,0,1,2,~{dirflag},~{fpsr},~{flags},~{memory}"( i64** %p2_addr, "=r,=*r,=*r,r,0,1,2,~{dirflag},~{fpsr},~{flags},~{memory}"( i64** %p2_addr,
i32* %lines, i64 256, i64* %p1, i64* %p2, i32 %tmp12 ) ; <i64*> [#uses=0] i32* %lines, i64 256, i64* %p1, i64* %p2, i32 %tmp12 ) ; <i64*> [#uses=0]
ret void ret void
} }

test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll

; RUN: llc < %s -relocation-model=static | FileCheck %s ; RUN: llc < %s -relocation-model=static -no-integrated-inline-as | FileCheck %s
; PR1761 ; PR1761
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-pc-linux" target triple = "x86_64-pc-linux"
@str = internal constant [12 x i8] c"init/main.c\00" ; <[12 x i8]*> [#uses=1] @str = internal constant [12 x i8] c"init/main.c\00" ; <[12 x i8]*> [#uses=1]
; CHECK: {{foo str$}} ; CHECK: {{foo str$}}
define i32 @unknown_bootoption() { define i32 @unknown_bootoption() {
entry: entry:
tail call void asm sideeffect "foo ${0:c}\0A", "i,~{dirflag},~{fpsr},~{flags}"( i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) ) tail call void asm sideeffect "foo ${0:c}\0A", "i,~{dirflag},~{fpsr},~{flags}"( i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) )
ret i32 undef ret i32 undef
} }

test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc -no-integrated-inline-as < %s | FileCheck %s
; PR2078 ; PR2078
; The clobber list says that "ax" is clobbered. Make sure that eax isn't ; The clobber list says that "ax" is clobbered. Make sure that eax isn't
; allocated to the input/output register. ; allocated to the input/output register.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8" target triple = "i386-apple-darwin8"
@pixels = weak global i32 0 ; <i32*> [#uses=2] @pixels = weak global i32 0 ; <i32*> [#uses=2]
define void @test() nounwind { define void @test() nounwind {
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test/CodeGen/X86/2008-02-26-AsmDirectMemOp.ll

; RUN: llc < %s -march=x86 ; RUN: llc < %s -march=x86 -no-integrated-inline-as
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-linux-gnu" target triple = "i386-pc-linux-gnu"
define void @dct_unquantize_h263_intra_mmx(i16* %block, i32 %n, i32 %qscale) nounwind { define void @dct_unquantize_h263_intra_mmx(i16* %block, i32 %n, i32 %qscale) nounwind {
entry: entry:
%tmp1 = shl i32 %qscale, 1 ; <i32> [#uses=1] %tmp1 = shl i32 %qscale, 1 ; <i32> [#uses=1]
br i1 false, label %bb46, label %bb59 br i1 false, label %bb46, label %bb59
bb46: ; preds = %entry bb46: ; preds = %entry
ret void ret void
bb59: ; preds = %entry bb59: ; preds = %entry
tail call void asm sideeffect "movd $1, %mm6 \0A\09packssdw %mm6, %mm6 \0A\09packssdw %mm6, %mm6 \0A\09movd $2, %mm5 \0A\09pxor %mm7, %mm7 \0A\09packssdw %mm5, %mm5 \0A\09packssdw %mm5, %mm5 \0A\09psubw %mm5, %mm7 \0A\09pxor %mm4, %mm4 \0A\09.align 1<<4\0A\091: \0A\09movq ($0, $3), %mm0 \0A\09movq 8($0, $3), %mm1 \0A\09pmullw %mm6, %mm0 \0A\09pmullw %mm6, %mm1 \0A\09movq ($0, $3), %mm2 \0A\09movq 8($0, $3), %mm3 \0A\09pcmpgtw %mm4, %mm2 \0A\09pcmpgtw %mm4, %mm3 \0A\09pxor %mm2, %mm0 \0A\09pxor %mm3, %mm1 \0A\09paddw %mm7, %mm0 \0A\09paddw %mm7, %mm1 \0A\09pxor %mm0, %mm2 \0A\09pxor %mm1, %mm3 \0A\09pcmpeqw %mm7, %mm0 \0A\09pcmpeqw %mm7, %mm1 \0A\09pandn %mm2, %mm0 \0A\09pandn %mm3, %mm1 \0A\09movq %mm0, ($0, $3) \0A\09movq %mm1, 8($0, $3) \0A\09add $$16, $3 \0A\09jng 1b \0A\09", "r,imr,imr,r,~{dirflag},~{fpsr},~{flags},~{memory}"( i16* null, i32 %tmp1, i32 0, i32 0 ) nounwind tail call void asm sideeffect "movd $1, %mm6 \0A\09packssdw %mm6, %mm6 \0A\09packssdw %mm6, %mm6 \0A\09movd $2, %mm5 \0A\09pxor %mm7, %mm7 \0A\09packssdw %mm5, %mm5 \0A\09packssdw %mm5, %mm5 \0A\09psubw %mm5, %mm7 \0A\09pxor %mm4, %mm4 \0A\09.align 1<<4\0A\091: \0A\09movq ($0, $3), %mm0 \0A\09movq 8($0, $3), %mm1 \0A\09pmullw %mm6, %mm0 \0A\09pmullw %mm6, %mm1 \0A\09movq ($0, $3), %mm2 \0A\09movq 8($0, $3), %mm3 \0A\09pcmpgtw %mm4, %mm2 \0A\09pcmpgtw %mm4, %mm3 \0A\09pxor %mm2, %mm0 \0A\09pxor %mm3, %mm1 \0A\09paddw %mm7, %mm0 \0A\09paddw %mm7, %mm1 \0A\09pxor %mm0, %mm2 \0A\09pxor %mm1, %mm3 \0A\09pcmpeqw %mm7, %mm0 \0A\09pcmpeqw %mm7, %mm1 \0A\09pandn %mm2, %mm0 \0A\09pandn %mm3, %mm1 \0A\09movq %mm0, ($0, $3) \0A\09movq %mm1, 8($0, $3) \0A\09add $$16, $3 \0A\09jng 1b \0A\09", "r,imr,imr,r,~{dirflag},~{fpsr},~{flags},~{memory}"( i16* null, i32 %tmp1, i32 0, i32 0 ) nounwind
ret void ret void
} }

test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc -no-integrated-inline-as < %s | FileCheck %s
; rdar://5720231 ; rdar://5720231
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin8" target triple = "i386-apple-darwin8"
define void @test() nounwind { define void @test() nounwind {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK-NOT: ret ; CHECK-NOT: ret
; CHECK: 1 $2 3 ; CHECK: 1 $2 3
; CHECK: ret ; CHECK: ret
tail call void asm sideeffect " ${0:c} $1 ${2:c} ", "imr,imr,i,~{dirflag},~{fpsr},~{flags}"( i32 1, i32 2, i32 3 ) nounwind tail call void asm sideeffect " ${0:c} $1 ${2:c} ", "imr,imr,i,~{dirflag},~{fpsr},~{flags}"( i32 1, i32 2, i32 3 ) nounwind
ret void ret void
} }

test/CodeGen/X86/2008-09-18-inline-asm-2.ll

; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 | FileCheck %s ; RUN: llc < %s -march=x86 -regalloc=fast -optimize-regalloc=0 -no-integrated-inline-as | FileCheck %s
; RUN: llc < %s -march=x86 -regalloc=basic | FileCheck %s ; RUN: llc < %s -march=x86 -regalloc=basic -no-integrated-inline-as | FileCheck %s
; RUN: llc < %s -march=x86 -regalloc=greedy | FileCheck %s ; RUN: llc < %s -march=x86 -regalloc=greedy -no-integrated-inline-as | FileCheck %s
; The 1st, 2nd, 3rd and 5th registers must all be different. The registers ; The 1st, 2nd, 3rd and 5th registers must all be different. The registers
; referenced in the 4th and 6th operands must not be the same as the 1st or 5th ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th
; operand. ; operand.
; ;
; CHECK: 1st=[[A1:%...]] ; CHECK: 1st=[[A1:%...]]
; CHECK-NOT: [[A1]] ; CHECK-NOT: [[A1]]
; CHECK: 2nd=[[A2:%...]] ; CHECK: 2nd=[[A2:%...]]
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test/CodeGen/X86/2008-10-17-Asm64bitRConstraint.ll

; RUN: llc < %s -march=x86 ; RUN: llc < %s -march=x86 -no-integrated-inline-as
; RUN: llc < %s -march=x86-64 ; RUN: llc < %s -march=x86-64 -no-integrated-inline-as
define void @test(i64 %x) nounwind { define void @test(i64 %x) nounwind {
entry: entry:
tail call void asm sideeffect "ASM: $0", "r,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind tail call void asm sideeffect "ASM: $0", "r,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
ret void ret void
} }

test/CodeGen/X86/2008-10-20-AsmDoubleInI32.ll

; RUN: llc < %s -march=x86 ; RUN: llc < %s -march=x86 -no-integrated-inline-as
; RUN: llc < %s -march=x86-64 ; RUN: llc < %s -march=x86-64 -no-integrated-inline-as
; from gcc.c-torture/compile/920520-1.c ; from gcc.c-torture/compile/920520-1.c
define i32 @g() nounwind { define i32 @g() nounwind {
entry: entry:
call void asm sideeffect "$0", "r"(double 1.500000e+00) nounwind call void asm sideeffect "$0", "r"(double 1.500000e+00) nounwind
ret i32 0 ret i32 0
} }

test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll

; RUN: llc < %s -march=x86 | FileCheck %s ; RUN: llc < %s -march=x86 -no-integrated-inline-as | FileCheck %s
; ModuleID = 'shant.c' ; ModuleID = 'shant.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.6" target triple = "i386-apple-darwin9.6"
define void @f() nounwind { define void @f() nounwind {
; CHECK-LABEL: f: ; CHECK-LABEL: f:
; CHECK-NOT: ret ; CHECK-NOT: ret
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test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll

; RUN: llc < %s -mtriple=i386-apple-darwin ; RUN: llc < %s -mtriple=i386-apple-darwin -no-integrated-inline-as
; rdar://6781755 ; rdar://6781755
; PR3934 ; PR3934
%0 = type { i32, i32 } ; type %0 %0 = type { i32, i32 } ; type %0
define void @bn_sqr_comba8(i32* nocapture %r, i32* %a) nounwind { define void @bn_sqr_comba8(i32* nocapture %r, i32* %a) nounwind {
entry: entry:
%asmtmp23 = tail call %0 asm "mulq $3", "={ax},={dx},{ax},*m,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32* %a) nounwind ; <%0> [#uses=1] %asmtmp23 = tail call %0 asm "mulq $3", "={ax},={dx},{ax},*m,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32* %a) nounwind ; <%0> [#uses=1]
%asmresult25 = extractvalue %0 %asmtmp23, 1 ; <i32> [#uses=1] %asmresult25 = extractvalue %0 %asmtmp23, 1 ; <i32> [#uses=1]
%asmtmp26 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={dx},=r,imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 %asmresult25, i32 0) nounwind ; <%0> [#uses=1] %asmtmp26 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={dx},=r,imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 %asmresult25, i32 0) nounwind ; <%0> [#uses=1]
%asmresult27 = extractvalue %0 %asmtmp26, 0 ; <i32> [#uses=1] %asmresult27 = extractvalue %0 %asmtmp26, 0 ; <i32> [#uses=1]
%asmtmp29 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={ax},={dx},imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 0, i32 %asmresult27) nounwind ; <%0> [#uses=0] %asmtmp29 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={ax},={dx},imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 0, i32 %asmresult27) nounwind ; <%0> [#uses=0]
ret void ret void
} }

test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll

; RUN: llc < %s -relocation-model=static | FileCheck %s ; RUN: llc < %s -relocation-model=static -no-integrated-inline-as | FileCheck %s
; PR4152 ; PR4152
; CHECK: {{1: ._pv_cpu_ops[+]8}} ; CHECK: {{1: ._pv_cpu_ops[+]8}}
; CHECK: {{2: ._G}} ; CHECK: {{2: ._G}}
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i386-apple-darwin9.6" target triple = "i386-apple-darwin9.6"
%struct.pv_cpu_ops = type { i32, [2 x i32] } %struct.pv_cpu_ops = type { i32, [2 x i32] }
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test/CodeGen/X86/2009-09-19-earlyclobber.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc -no-integrated-inline-as < %s | FileCheck %s
; ModuleID = '4964.c' ; ModuleID = '4964.c'
; PR 4964 ; PR 4964
; Registers other than RAX, RCX are OK, but they must be different. ; Registers other than RAX, RCX are OK, but they must be different.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin10.0" target triple = "x86_64-apple-darwin10.0"
%0 = type { i64, i64 } ; type %0 %0 = type { i64, i64 } ; type %0
define i64 @flsst(i64 %find) nounwind ssp { define i64 @flsst(i64 %find) nounwind ssp {
entry: entry:
; CHECK: FOO %rax %rcx ; CHECK: FOO %rax %rcx
%asmtmp = tail call %0 asm sideeffect "FOO $0 $1 $2", "=r,=&r,rm,~{dirflag},~{fpsr},~{flags},~{cc}"(i64 %find) nounwind ; <%0> [#uses=1] %asmtmp = tail call %0 asm sideeffect "FOO $0 $1 $2", "=r,=&r,rm,~{dirflag},~{fpsr},~{flags},~{cc}"(i64 %find) nounwind ; <%0> [#uses=1]
%asmresult = extractvalue %0 %asmtmp, 0 ; <i64> [#uses=1] %asmresult = extractvalue %0 %asmtmp, 0 ; <i64> [#uses=1]
ret i64 %asmresult ret i64 %asmresult
} }

test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-inline-as | FileCheck %s
; pr5391 ; pr5391
define void @t() nounwind ssp { define void @t() nounwind ssp {
entry: entry:
; CHECK-LABEL: t: ; CHECK-LABEL: t:
; CHECK: movl %ecx, %eax ; CHECK: movl %ecx, %eax
; CHECK: %eax = foo (%eax, %ecx) ; CHECK: %eax = foo (%eax, %ecx)
%b = alloca i32 ; <i32*> [#uses=2] %b = alloca i32 ; <i32*> [#uses=2]
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test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll

; RUN: llc < %s -O0 -regalloc=fast | FileCheck %s ; RUN: llc < %s -O0 -regalloc=fast -no-integrated-inline-as | FileCheck %s
; PR6520 ; PR6520
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
target triple = "i386-apple-darwin10.0.0" target triple = "i386-apple-darwin10.0.0"
%0 = type { i8*, i8*, i32 } %0 = type { i8*, i8*, i32 }
define i8* @func() nounwind ssp { define i8* @func() nounwind ssp {
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test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll

; RUN: llc -regalloc=fast -optimize-regalloc=0 < %s | FileCheck %s ; RUN: llc -regalloc=fast -optimize-regalloc=0 -no-integrated-inline-as < %s | FileCheck %s
; PR7382 ; PR7382
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
@.str = private constant [23 x i8] c"This should be -1: %d\0A\00" ; <[23 x i8]*> [#uses=1] @.str = private constant [23 x i8] c"This should be -1: %d\0A\00" ; <[23 x i8]*> [#uses=1]
define i32 @main() { define i32 @main() {
entry: entry:
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test/CodeGen/X86/2010-06-25-asm-RA-crash.ll

; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32 ; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32 -no-integrated-inline-as
%struct.__SEH2Frame = type {} %struct.__SEH2Frame = type {}
define void @_SEH2FrameHandler() nounwind { define void @_SEH2FrameHandler() nounwind {
entry: entry:
%target.addr.i = alloca i8*, align 4 ; <i8**> [#uses=2] %target.addr.i = alloca i8*, align 4 ; <i8**> [#uses=2]
%frame = alloca %struct.__SEH2Frame*, align 4 ; <%struct.__SEH2Frame**> [#uses=1] %frame = alloca %struct.__SEH2Frame*, align 4 ; <%struct.__SEH2Frame**> [#uses=1]
%tmp = load %struct.__SEH2Frame** %frame ; <%struct.__SEH2Frame*> [#uses=1] %tmp = load %struct.__SEH2Frame** %frame ; <%struct.__SEH2Frame*> [#uses=1]
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test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll

; RUN: llc < %s -march=x86 -O0 | FileCheck %s ; RUN: llc < %s -march=x86 -O0 -no-integrated-inline-as | FileCheck %s
; PR7509 ; PR7509
target triple = "i386-apple-darwin10" target triple = "i386-apple-darwin10"
%asmtype = type { i32, i8*, i32, i32 } %asmtype = type { i32, i8*, i32, i32 }
; Arguments 1 and 4 must be the same. No other output arguments may be ; Arguments 1 and 4 must be the same. No other output arguments may be
; allocated %eax. ; allocated %eax.
; CHECK: InlineAsm Start ; CHECK: InlineAsm Start
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test/CodeGen/X86/2010-06-28-matched-g-constraint.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -no-integrated-inline-as | FileCheck %s
; Any register is OK for %0, but it must be a register, not memory. ; Any register is OK for %0, but it must be a register, not memory.
define i32 @foo() nounwind ssp { define i32 @foo() nounwind ssp {
entry: entry:
; CHECK: GCROOT %eax ; CHECK: GCROOT %eax
%_r = alloca i32, align 4 ; <i32*> [#uses=2] %_r = alloca i32, align 4 ; <i32*> [#uses=2]
call void asm "/* GCROOT $0 */", "=*imr,0,~{dirflag},~{fpsr},~{flags}"(i32* %_r, i32 4) nounwind call void asm "/* GCROOT $0 */", "=*imr,0,~{dirflag},~{fpsr},~{flags}"(i32* %_r, i32 4) nounwind
%0 = load i32* %_r, align 4 ; <i32> [#uses=1] %0 = load i32* %_r, align 4 ; <i32> [#uses=1]
ret i32 %0 ret i32 %0
} }

test/CodeGen/X86/2010-07-02-asm-alignstack.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -no-integrated-inline-as | FileCheck %s
define void @foo() nounwind ssp { define void @foo() nounwind ssp {
entry: entry:
; CHECK: foo ; CHECK: foo
; CHECK: pushq ; CHECK: pushq
; CHECK: int $3 ; CHECK: int $3
call void asm sideeffect alignstack "# top of block", "~{dirflag},~{fpsr},~{flags},~{edi},~{esi},~{edx},~{ecx},~{eax}"() nounwind call void asm sideeffect alignstack "# top of block", "~{dirflag},~{fpsr},~{flags},~{edi},~{esi},~{edx},~{ecx},~{eax}"() nounwind
call void asm sideeffect alignstack ".file \22small.c\22", "~{dirflag},~{fpsr},~{flags}"() nounwind call void asm sideeffect alignstack ".file \22small.c\22", "~{dirflag},~{fpsr},~{flags}"() nounwind
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test/CodeGen/X86/2010-07-06-asm-RIP.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-inline-as | FileCheck %s
; PR 4752 ; PR 4752
@n = global i32 0 ; <i32*> [#uses=2] @n = global i32 0 ; <i32*> [#uses=2]
define void @f(i32*) nounwind ssp { define void @f(i32*) nounwind ssp {
ret void ret void
} }
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test/CodeGen/X86/2010-07-13-indirectXconstraint.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -no-integrated-inline-as | FileCheck %s
; PR 7528 ; PR 7528
; formerly crashed ; formerly crashed
%0 = type { [12 x i16] } %0 = type { [12 x i16] }
%union..0anon = type { [3 x <1 x i64>] } %union..0anon = type { [3 x <1 x i64>] }
@gsm_H.1466 = internal constant %0 { [12 x i16] [i16 -134, i16 -374, i16 0, i16 2054, i16 5741, i16 8192, i16 5741, i16 2054, i16 0, i16 -374, i16 -134, i16 0] }, align 8 ; <%0*> [#uses=1] @gsm_H.1466 = internal constant %0 { [12 x i16] [i16 -134, i16 -374, i16 0, i16 2054, i16 5741, i16 8192, i16 5741, i16 2054, i16 0, i16 -374, i16 -134, i16 0] }, align 8 ; <%0*> [#uses=1]
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test/CodeGen/X86/2011-10-11-SpillDead.ll

; RUN: llc < %s -verify-regalloc ; RUN: llc < %s -verify-regalloc -no-integrated-inline-as
; PR11125 ; PR11125
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.7" target triple = "x86_64-apple-macosx10.7"
; The inline asm takes %x as a GR32_ABCD virtual register. ; The inline asm takes %x as a GR32_ABCD virtual register.
; The call to @g forces a spill of that register. ; The call to @g forces a spill of that register.
; ;
; The asm has a dead output tied to %x. ; The asm has a dead output tied to %x.
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test/CodeGen/X86/asm-block-labels.ll

; RUN: opt < %s -std-compile-opts | llc ; RUN: opt < %s -std-compile-opts | llc -no-integrated-inline-as
; ModuleID = 'block12.c' ; ModuleID = 'block12.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "i686-apple-darwin8" target triple = "i686-apple-darwin8"
define void @bar() { define void @bar() {
entry: entry:
br label %"LASM$foo" br label %"LASM$foo"
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test/CodeGen/X86/asm-global-imm.ll

; RUN: llc < %s -march=x86 -relocation-model=static | FileCheck %s ; RUN: llc < %s -march=x86 -relocation-model=static -no-integrated-inline-as | FileCheck %s
; PR882 ; PR882
target datalayout = "e-p:32:32" target datalayout = "e-p:32:32"
target triple = "i686-apple-darwin9.0.0d2" target triple = "i686-apple-darwin9.0.0d2"
@GV = weak global i32 0 ; <i32*> [#uses=2] @GV = weak global i32 0 ; <i32*> [#uses=2]
@str = external global [12 x i8] ; <[12 x i8]*> [#uses=1] @str = external global [12 x i8] ; <[12 x i8]*> [#uses=1]
define void @foo() { define void @foo() {
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test/CodeGen/X86/cas.ll

; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - | FileCheck %s ; RUN: llc -mtriple=x86_64-pc-linux-gnu %s -o - -no-integrated-inline-as | FileCheck %s
; C code this came from ; C code this came from
;bool cas(float volatile *p, float *expected, float desired) { ;bool cas(float volatile *p, float *expected, float desired) {
; bool success; ; bool success;
; __asm__ __volatile__("lock; cmpxchg %[desired], %[mem]; " ; __asm__ __volatile__("lock; cmpxchg %[desired], %[mem]; "
; "mov %[expected], %[expected_out]; " ; "mov %[expected], %[expected_out]; "
; "sete %[success]" ; "sete %[success]"
; : [success] "=a" (success), ; : [success] "=a" (success),
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test/CodeGen/X86/fast-isel.ll

; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2 ; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -march=x86 -mattr=sse2 -no-integrated-inline-as
; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10 ; RUN: llc < %s -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=x86_64-apple-darwin10 -no-integrated-inline-as
; This tests very minimal fast-isel functionality. ; This tests very minimal fast-isel functionality.
define i32* @foo(i32* %p, i32* %q, i32** %z) nounwind { define i32* @foo(i32* %p, i32* %q, i32** %z) nounwind {
entry: entry:
%r = load i32* %p %r = load i32* %p
%s = load i32* %q %s = load i32* %q
%y = load i32** %z %y = load i32** %z
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test/CodeGen/X86/fold-xmm-zero.ll

; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 | FileCheck %s ; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 -no-integrated-inline-as | FileCheck %s
; Simple test to make sure folding for special constants (like float zero) ; Simple test to make sure folding for special constants (like float zero)
; isn't completely broken. ; isn't completely broken.
; CHECK: divss LCPI0 ; CHECK: divss LCPI0
%0 = type { float, float, float, float, float, float, float, float } %0 = type { float, float, float, float, float, float, float, float }
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test/CodeGen/X86/inline-asm-flag-clobber.ll

; RUN: llc -march=x86-64 < %s | FileCheck %s ; RUN: llc -march=x86-64 -no-integrated-inline-as < %s | FileCheck %s
; PR3701 ; PR3701
define i64 @t(i64* %arg) nounwind { define i64 @t(i64* %arg) nounwind {
br i1 true, label %1, label %5 br i1 true, label %1, label %5
; <label>:1 ; preds = %0 ; <label>:1 ; preds = %0
%2 = icmp eq i64* null, %arg ; <i1> [#uses=1] %2 = icmp eq i64* null, %arg ; <i1> [#uses=1]
%3 = tail call i64* asm sideeffect "movl %fs:0,$0", "=r,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%struct.thread*> [#uses=0] %3 = tail call i64* asm sideeffect "movl %fs:0,$0", "=r,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%struct.thread*> [#uses=0]
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test/CodeGen/X86/inline-asm-fpstack.ll

; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin | FileCheck %s ; RUN: llc < %s -mcpu=generic -mtriple=i386-apple-darwin -no-integrated-inline-as | FileCheck %s
; There should be no stack manipulations between the inline asm and ret. ; There should be no stack manipulations between the inline asm and ret.
; CHECK: test1 ; CHECK: test1
; CHECK: InlineAsm End ; CHECK: InlineAsm End
; CHECK-NEXT: ret ; CHECK-NEXT: ret
define x86_fp80 @test1() { define x86_fp80 @test1() {
%tmp85 = call x86_fp80 asm sideeffect "fld0", "={st(0)}"() %tmp85 = call x86_fp80 asm sideeffect "fld0", "={st(0)}"()
ret x86_fp80 %tmp85 ret x86_fp80 %tmp85
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test/CodeGen/X86/inline-asm-h.ll

; RUN: llc -mtriple=x86_64-pc-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=x86_64-pc-linux-gnu < %s | FileCheck %s
@foobar = common global i32 0, align 4 @foobar = common global i32 0, align 4
define void @zed() nounwind { define void @zed() nounwind {
entry: entry:
call void asm "movq %mm2,${0:H}", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* @foobar) nounwind call void asm "movq %mm2,${0:H}", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* @foobar) nounwind
ret void ret void
} }
; CHECK: zed ; CHECK: zed
; CHECK: movq %mm2,foobar+8(%rip) ; CHECK: movq %mm2, foobar+8(%rip)

test/CodeGen/X86/inline-asm-modifier-n.ll

; RUN: llc < %s -march=x86 | grep " 37" ; RUN: llc < %s -march=x86 -no-integrated-inline-as | grep " 37"
; rdar://7008959 ; rdar://7008959
define void @bork() nounwind { define void @bork() nounwind {
entry: entry:
tail call void asm sideeffect "BORK ${0:n}", "i,~{dirflag},~{fpsr},~{flags}"(i32 -37) nounwind tail call void asm sideeffect "BORK ${0:n}", "i,~{dirflag},~{fpsr},~{flags}"(i32 -37) nounwind
ret void ret void
} }

test/CodeGen/X86/inline-asm-mrv.ll

; PR2094 ; PR2094
; RUN: llc < %s -march=x86-64 | grep movslq ; RUN: llc < %s -march=x86-64 -no-integrated-inline-as | grep movslq
; RUN: llc < %s -march=x86-64 | grep addps ; RUN: llc < %s -march=x86-64 -no-integrated-inline-as | grep addps
; RUN: llc < %s -march=x86-64 | grep paddd ; RUN: llc < %s -march=x86-64 -no-integrated-inline-as | grep paddd
; RUN: llc < %s -march=x86-64 | not grep movq ; RUN: llc < %s -march=x86-64 -no-integrated-inline-as | not grep movq
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8" target triple = "x86_64-apple-darwin8"
define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind { define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind {
%tmp12 = sext i32 %stride to i64 ; <i64> [#uses=1] %tmp12 = sext i32 %stride to i64 ; <i64> [#uses=1]
%mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6", %mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6",
"=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind "=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind
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test/CodeGen/X86/inline-asm-q-regs.ll

; RUN: llc < %s -march=x86-64 -mattr=+avx ; RUN: llc < %s -march=x86-64 -mattr=+avx -no-integrated-inline-as
; rdar://7066579 ; rdar://7066579
%0 = type { i64, i64, i64, i64, i64 } ; type %0 %0 = type { i64, i64, i64, i64, i64 } ; type %0
define void @test1() nounwind { define void @test1() nounwind {
entry: entry:
%asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0] %asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0]
ret void ret void
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test/CodeGen/X86/inline-asm-stack-realign3.ll

; RUN: llc -march=x86 < %s | FileCheck %s ; RUN: llc -march=x86 -no-integrated-inline-as < %s | FileCheck %s
declare void @bar(i32* %junk) declare void @bar(i32* %junk)
define i32 @foo(i1 %cond) { define i32 @foo(i1 %cond) {
entry: entry:
%r = alloca i32, align 128 %r = alloca i32, align 128
store i32 -1, i32* %r, align 128 store i32 -1, i32* %r, align 128
br i1 %cond, label %doit, label %skip br i1 %cond, label %doit, label %skip
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test/CodeGen/X86/inline-asm-tied.ll

; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic | FileCheck %s ; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic -no-integrated-inline-as | FileCheck %s
; rdar://6992609 ; rdar://6992609
; CHECK: movl [[EDX:%e..]], 4(%esp) ; CHECK: movl [[EDX:%e..]], 4(%esp)
; CHECK: movl [[EDX]], 4(%esp) ; CHECK: movl [[EDX]], 4(%esp)
target triple = "i386-apple-darwin9.0" target triple = "i386-apple-darwin9.0"
@llvm.used = appending global [1 x i8*] [i8* bitcast (i64 (i64)* @_OSSwapInt64 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] @llvm.used = appending global [1 x i8*] [i8* bitcast (i64 (i64)* @_OSSwapInt64 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
define i64 @_OSSwapInt64(i64 %_data) nounwind { define i64 @_OSSwapInt64(i64 %_data) nounwind {
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test/CodeGen/X86/inline-asm-x-scalar.ll

; RUN: llc < %s -march=x86 -mcpu=yonah ; RUN: llc < %s -march=x86 -mcpu=yonah -no-integrated-inline-as
define void @test1() { define void @test1() {
tail call void asm sideeffect "ucomiss $0", "x"( float 0x41E0000000000000) tail call void asm sideeffect "ucomiss $0", "x"( float 0x41E0000000000000)
ret void ret void
} }
define void @test2() { define void @test2() {
%tmp53 = tail call i32 asm "ucomiss $1, $3\0Acmovae $2, $0 ", "=r,mx,mr,x,0,~{dirflag},~{fpsr},~{flags},~{cc}"( float 0x41E0000000000000, i32 2147483647, float 0.000000e+00, i32 0 ) ; <i32> [#uses %tmp53 = tail call i32 asm "ucomiss $1, $3\0Acmovae $2, $0 ", "=r,mx,mr,x,0,~{dirflag},~{fpsr},~{flags},~{cc}"( float 0x41E0000000000000, i32 2147483647, float 0.000000e+00, i32 0 ) ; <i32> [#uses
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test/CodeGen/X86/inline-asm.ll

; RUN: llc < %s -march=x86 ; RUN: llc < %s -march=x86 -no-integrated-inline-as
define i32 @test1() nounwind { define i32 @test1() nounwind {
; Dest is AX, dest type = i32. ; Dest is AX, dest type = i32.
%tmp4 = call i32 asm sideeffect "FROB $0", "={ax}"() %tmp4 = call i32 asm sideeffect "FROB $0", "={ax}"()
ret i32 %tmp4 ret i32 %tmp4
} }
define void @test2(i32 %V) nounwind { define void @test2(i32 %V) nounwind {
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test/CodeGen/X86/ms-inline-asm.ll

; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s ; RUN: llc < %s -march=x86 -mcpu=core2 -no-integrated-inline-as | FileCheck %s
define i32 @t1() nounwind { define i32 @t1() nounwind {
entry: entry:
%0 = tail call i32 asm sideeffect inteldialect "mov eax, $1\0A\09mov $0, eax", "=r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind %0 = tail call i32 asm sideeffect inteldialect "mov eax, $1\0A\09mov $0, eax", "=r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32 1) nounwind
ret i32 %0 ret i32 %0
; CHECK: t1 ; CHECK: t1
; CHECK: {{## InlineAsm Start|#APP}} ; CHECK: {{## InlineAsm Start|#APP}}
; CHECK: .intel_syntax ; CHECK: .intel_syntax
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test/CodeGen/X86/mult-alt-generic-i686.ll

; RUN: llc < %s -march=x86 ; RUN: llc < %s -march=x86 -no-integrated-inline-as
; ModuleID = 'mult-alt-generic.c' ; ModuleID = 'mult-alt-generic.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
target triple = "i686" target triple = "i686"
@mout0 = common global i32 0, align 4 @mout0 = common global i32 0, align 4
@min1 = common global i32 0, align 4 @min1 = common global i32 0, align 4
@marray = common global [2 x i32] zeroinitializer, align 4 @marray = common global [2 x i32] zeroinitializer, align 4
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test/CodeGen/X86/mult-alt-generic-x86_64.ll

; RUN: llc < %s -march=x86-64 ; RUN: llc < %s -march=x86-64 -no-integrated-inline-as
; ModuleID = 'mult-alt-generic.c' ; ModuleID = 'mult-alt-generic.c'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64" target triple = "x86_64"
@mout0 = common global i32 0, align 4 @mout0 = common global i32 0, align 4
@min1 = common global i32 0, align 4 @min1 = common global i32 0, align 4
@marray = common global [2 x i32] zeroinitializer, align 4 @marray = common global [2 x i32] zeroinitializer, align 4
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test/CodeGen/X86/mult-alt-x86.ll

; RUN: llc < %s -march=x86 -mattr=+sse2 ; RUN: llc < %s -march=x86 -mattr=+sse2 -no-integrated-inline-as
; ModuleID = 'mult-alt-x86.c' ; ModuleID = 'mult-alt-x86.c'
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
target triple = "i686-pc-win32" target triple = "i686-pc-win32"
@mout0 = common global i32 0, align 4 @mout0 = common global i32 0, align 4
@min1 = common global i32 0, align 4 @min1 = common global i32 0, align 4
@dout0 = common global double 0.000000e+000, align 8 @dout0 = common global double 0.000000e+000, align 8
@din1 = common global double 0.000000e+000, align 8 @din1 = common global double 0.000000e+000, align 8
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test/CodeGen/X86/multiple-loop-post-inc.ll

; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem < %s | FileCheck %s ; RUN: llc -asm-verbose=false -disable-branch-fold -disable-block-placement -disable-tail-duplicate -march=x86-64 -mcpu=nehalem -no-integrated-inline-as < %s | FileCheck %s
; rdar://7236213 ; rdar://7236213
; ;
; The scheduler's 2-address hack has been disabled, so there is ; The scheduler's 2-address hack has been disabled, so there is
; currently no good guarantee that this test will pass until the ; currently no good guarantee that this test will pass until the
; machine scheduler develops an equivalent heuristic. ; machine scheduler develops an equivalent heuristic.
; CodeGen shouldn't require any lea instructions inside the marked loop. ; CodeGen shouldn't require any lea instructions inside the marked loop.
; It should properly set up post-increment uses and do coalescing for ; It should properly set up post-increment uses and do coalescing for
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test/Transforms/BranchFolding/2007-10-19-InlineAsmDirectives.ll

; RUN: opt < %s -std-compile-opts -o - | llc -o - | grep bork_directive | wc -l | grep 2 ; RUN: opt < %s -std-compile-opts -o - | llc -no-integrated-inline-as -o - | grep bork_directive | wc -l | grep 2
;; We don't want branch folding to fold asm directives. ;; We don't want branch folding to fold asm directives.
define void @bork(i32 %param) { define void @bork(i32 %param) {
entry: entry:
%tmp = icmp eq i32 %param, 0 %tmp = icmp eq i32 %param, 0
br i1 %tmp, label %cond_true, label %cond_false br i1 %tmp, label %cond_true, label %cond_false
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