[X86] AVX512 fallback for floating-point scalar selects

[zvi]

Summary

In the case where of 'select i1 , f32, f32' or select i1, f64, f64 prefer lowering to masked-moves over branches.

Fixes pr30561

[delena]

I'm not sure that RHS code is better than LHS.
I assume that this case should give better results:

define float @pr30561_f32(float %a, float %b, double %c, double %d) {

%c = fcmp oeq double %c, %d
%cond = select i1 %c, float %a, float %b
ret float %cond

}

[zvi]

In D25310#563215, @delena wrote:

I'm not sure that RHS code is better than LHS.

After a consultation i believe that the RHS is at least as good as in the LHS, and in cases of branch-mispredictions the RHS is much better.

I assume that this case should give better results:

define float @pr30561_f32(float %a, float %b, double %c, double %d) {

%c = fcmp oeq double %c, %d
%cond = select i1 %c, float %a, float %b
ret float %cond

}

Note that the case in your example is already handled in line 16023.

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

if (SSECC != 8) {
                            VSel, DAG.getIntPtrConstant(0, DL));
       }
       SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
       SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
       return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
     }
   }
 
+  // AVX512 fallback is to lower selects of scalar floats to masked moves.
+  if (Cond.getValueType() == MVT::i1 && (VT == MVT::f64 || VT == MVT::f32) &&
+      Subtarget.hasAVX512())
+    return DAG.getNode(X86ISD::SELECTS, DL, VT, Cond, Op1, Op2);
+
   if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
     SDValue Op1Scalar;
     if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
       Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
     else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
       Op1Scalar = Op1.getOperand(0);
     SDValue Op2Scalar;
     if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))

llvm/trunk/test/CodeGen/X86/avx512-select.ll

 ; CHECK-NEXT:    cmpb $1, %cl
 ; CHECK-NEXT:    movl $1, %eax
 ; CHECK-NEXT:    adcxq %rcx, %rax
 ; CHECK-NEXT:    retq
   %v = select i1 undef , i64 1, i64 2
   ret i64 %v
 }
 
-define double @pr30561_f64(double %a, double %b, i1 %c) {
+define double @pr30561_f64(double %b, double %a, i1 %c) {
 ; CHECK-LABEL: pr30561_f64:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    jne LBB11_2
-; CHECK-NEXT:  ## BB#1:
-; CHECK-NEXT:    vmovaps %xmm1, %xmm0
-; CHECK-NEXT:  LBB11_2:
+; CHECK-NEXT:    andl $1, %edi
+; CHECK-NEXT:    kmovw %edi, %k1
+; CHECK-NEXT:    vmovsd %xmm1, %xmm0, %xmm0 {%k1}
 ; CHECK-NEXT:    retq
   %cond = select i1 %c, double %a, double %b
   ret double %cond
 }
 
-define float @pr30561_f32(float %a, float %b, i1 %c) {
+define float @pr30561_f32(float %b, float %a, i1 %c) {
 ; CHECK-LABEL: pr30561_f32:
 ; CHECK:       ## BB#0:
-; CHECK-NEXT:    testb $1, %dil
-; CHECK-NEXT:    jne LBB12_2
-; CHECK-NEXT:  ## BB#1:
-; CHECK-NEXT:    vmovaps %xmm1, %xmm0
-; CHECK-NEXT:  LBB12_2:
+; CHECK-NEXT:    andl $1, %edi
+; CHECK-NEXT:    kmovw %edi, %k1
+; CHECK-NEXT:    vmovss %xmm1, %xmm0, %xmm0 {%k1}
 ; CHECK-NEXT:    retq
   %cond = select i1 %c, float %a, float %b
   ret float %cond
 }