[X86] Optimization for replacing LEA with MOV at frame index elimination time

[zvi]

Summary

Replace a LEA instruction of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'

MOV is preferable over LEA because usually there are more issue-slots available to execute MOVs than LEAs. Latest processors also support zero-latency MOVs.

Fixes pr29022.

[mkuper]

Thanks, Zvi!

lib/Target/X86/X86RegisterInfo.cpp

599

This should be 'mov %esp, %ebx', without the parens.

606

Are you absolutely sure all the operand that you getReg() here must be isReg()?

618

I'm not sure this is correct.

If I understand the semantics correctly, LEA is special in that if the operand size is 64 bit, and the address size is 32-bit, it will only set the low dword bits of the source, and zero-extend. This will not happen if you do a 64-to-64-bit MOV.

628

Have you made sure there are no iterator invalidation issues here? This gets called while iterating over the basic block.

[zvi]

Thanks for the thorough review, Michael. I Will upload a revised patch,

lib/Target/X86/X86RegisterInfo.cpp

599

Good catch!

606

The use operands are defined as:
def lea64_32mem : Operand<i32> {
...

let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG);

...
}

618

Yeah this incorrect. Thanks for catching that.

628

Will check this.
I noticed that AArch64RegisterInfo::eliminateFrameIndex() calls rewriteAArch64FrameIndex() which calls MI.eraseFromParent() and for PPC there is a similar flow - not that this proves anything.

[zvi]

New revision addresses all Michael's comments except for the question whether erasing an instruction will invalidate an iterator - i am still looking into this.

[mkuper]

LGTM

lib/Target/X86/X86RegisterInfo.cpp

 
 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
                                            unsigned Reg, int &FrameIdx) const {
   // Since X86 defines assignCalleeSavedSpillSlots which always return true
   // this function neither used nor tested.
   llvm_unreachable("Unused function on X86. Otherwise need a test case.");
 }
 
+// tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
+// of the form 'lea (%esp), %ebx' --> 'mov (%esp), %ebx'.
+// TODO: In this case we should be really trying first to entirely eliminate
+// this instruction which is a plain copy.
+static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II) {
+  MachineInstr &MI = *II;
+  unsigned Opc = II->getOpcode();
+  // Check if this is a LEA of the form 'lea (%esp), %ebx'
+  if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
+      MI.getOperand(2).getImm() != 1 ||
+      MI.getOperand(3).getReg() != X86::NoRegister ||
+      MI.getOperand(4).getImm() != 0 ||
+      MI.getOperand(5).getReg() != X86::NoRegister)
+    return false;
+  unsigned BasePtr = MI.getOperand(1).getReg();
+  unsigned NewDestReg = MI.getOperand(0).getReg();
+  unsigned NewOpc = Opc == X86::LEA32r ? X86::MOV32rr : X86::MOV64rr;
+  if (Opc == X86::LEA64_32r) {
+    // Need to ensure both register operands are 64-bit registers. See comment
+    // in eliminateFrameIndex on why this can and should be done.
+    assert(X86::GR64RegClass.contains(BasePtr) &&
+           "Base pointer operand of LEA64_32r was expected to "
+           "be a 64-bit register");
+    if (X86::GR32RegClass.contains(MI.getOperand(0).getReg()))
+      NewDestReg = getX86SubSuperRegister(MI.getOperand(0).getReg(), 64);
+  }
+  const X86InstrInfo *TII =
+      MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
+  BuildMI(*MI.getParent(), II, MI.getDebugLoc(), TII->get(NewOpc), NewDestReg)
+      .addReg(BasePtr);
+  II->getParent()->erase(II);
+  return true;
+}
+
 void
 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                      int SPAdj, unsigned FIOperandNum,
                                      RegScavenger *RS) const {
   MachineInstr &MI = *II;
   MachineFunction &MF = *MI.getParent()->getParent();
   const X86FrameLowering *TFI = getFrameLowering(MF);
   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   }
 
   if (MI.getOperand(FIOperandNum+3).isImm()) {
     // Offset is a 32-bit integer.
     int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
     int Offset = FIOffset + Imm;
     assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
            "Requesting 64-bit offset in 32-bit immediate!");
+    if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
       MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
   } else {
     // Offset is symbolic. This is extremely rare.
     uint64_t Offset = FIOffset +
       (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
     MI.getOperand(FIOperandNum + 3).setOffset(Offset);
   }
 }
 

test/CodeGen/X86/avx-intel-ocl.ll

 ; Push is not deemed profitable if we're realigning the stack.
 ; X32: {{pushl|movl}}   %eax
 ; X32: call
 ; X32: ret
 
 ; X64-LABEL: testf16_inp
 ; X64: vaddps  {{.*}}, {{%ymm[0-1]}}
 ; X64: vaddps  {{.*}}, {{%ymm[0-1]}}
-; X64: leaq    {{.*}}(%rsp), %rdi
+; X64: movq    %rsp, %rdi
 ; X64: call
 ; X64: ret
 
 ;test calling conventions - input parameters
 define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind {
   %y = alloca <16 x float>, align 16
   %x = fadd <16 x float> %a, %b
   %1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)

test/CodeGen/X86/avx512-intel-ocl.ll

 ; X32: vaddps  {{.*}}, {{%zmm[0-1]}}
 ; Push is not deemed profitable if we're realigning the stack.
 ; X32: {{pushl|movl}}   %eax
 ; X32: call
 ; X32: ret
 
 ; X64-LABEL: testf16_inp
 ; X64: vaddps  {{.*}}, {{%zmm[0-1]}}
-; X64: leaq    {{.*}}(%rsp), %rdi
+; X64: movq    %rsp, %rdi
 ; X64: call
 ; X64: ret
 
 ;test calling conventions - input parameters
 define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind {
   %y = alloca <16 x float>, align 16
   %x = fadd <16 x float> %a, %b
   %1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y)

test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll

 ; RUN: llc -march=x86-64 -mtriple=x86_64-linux < %s | FileCheck %s
 ; RUN: opt -strip-debug < %s | llc -march=x86-64 -mtriple=x86_64-linux | FileCheck %s
 ; http://llvm.org/PR19051. Minor code-motion difference with -g.
 ; Presence of debug info shouldn't affect the codegen. Make sure that
 ; we generated the same code sequence with and without debug info. 
 ;
 ; CHECK:      callq   _Z3fooPcjPKc
 ; CHECK:      callq   _Z3fooPcjPKc
-; CHECK:      leaq    (%rsp), %rdi
+; CHECK:      movq    %rsp, %rdi
 ; CHECK:      movl    $4, %esi
 ; CHECK:      testl   {{%[a-z]+}}, {{%[a-z]+}}
 ; CHECK:      je     .LBB0_4
 
 ; Regenerate test with this command: 
 ;   clang++ -emit-llvm -S -O2 -g
 ; from this source:
 ;

test/CodeGen/X86/dynamic-allocas-VLAs.ll

 
 ; CHECK: _t2
 ; CHECK: pushq %rbp
 ; CHECK: movq %rsp, %rbp
 ; CHECK: andq $-32, %rsp
 ; CHECK: subq ${{[0-9]+}}, %rsp
 ;
 ; CHECK: leaq {{[0-9]*}}(%rsp), %rdi
-; CHECK: leaq {{[0-9]*}}(%rsp), %rsi
+; CHECK: movq %rsp, %rsi
 ; CHECK: callq _t2_helper
 ;
 ; CHECK: movq %rbp, %rsp
 ; CHECK: popq %rbp
 }
 
 declare void @t2_helper(i32*, <8 x float>*)
 

 ; CHECK: pushq %rbp
 ; CHECK: movq %rsp, %rbp
 ; CHECK: pushq %rbx
 ; CHECK: andq $-32, %rsp
 ; CHECK: subq ${{[0-9]+}}, %rsp
 ; CHECK: movq %rsp, %rbx
 ;
 ; CHECK: leaq {{[0-9]*}}(%rbx), %rdi
-; CHECK: leaq {{[0-9]*}}(%rbx), %rdx
+; CHECK: movq %rbx, %rdx
 ; CHECK: callq   _t4_helper
 ;
 ; CHECK: leaq -{{[0-9]+}}(%rbp), %rsp
 ; CHECK: popq %rbx
 ; CHECK: popq %rbp
 }
 
 declare void @t4_helper(i32*, i32*, <8 x float>*)

test/CodeGen/X86/extractelement-index.ll

 ; SSE-LABEL: extractelement_v32i8_var:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pushq %rbp
 ; SSE-NEXT:    movq %rsp, %rbp
 ; SSE-NEXT:    andq $-32, %rsp
 ; SSE-NEXT:    subq $64, %rsp
 ; SSE-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
 ; SSE-NEXT:    movaps %xmm0, (%rsp)
-; SSE-NEXT:    leaq (%rsp), %rax
+; SSE-NEXT:    movq %rsp, %rax
 ; SSE-NEXT:    movb (%rdi,%rax), %al
 ; SSE-NEXT:    movq %rbp, %rsp
 ; SSE-NEXT:    popq %rbp
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: extractelement_v32i8_var:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    pushq %rbp
 ; AVX-NEXT:    movq %rsp, %rbp
 ; AVX-NEXT:    andq $-32, %rsp
 ; AVX-NEXT:    subq $64, %rsp
 ; AVX-NEXT:    vmovaps %ymm0, (%rsp)
-; AVX-NEXT:    leaq (%rsp), %rax
+; AVX-NEXT:    movq %rsp, %rax
 ; AVX-NEXT:    movb (%rdi,%rax), %al
 ; AVX-NEXT:    movq %rbp, %rsp
 ; AVX-NEXT:    popq %rbp
 ; AVX-NEXT:    vzeroupper
 ; AVX-NEXT:    retq
   %b = extractelement <32 x i8> %a, i256 %i
   ret i8 %b
 }

test/CodeGen/X86/fast-isel-x86-64.ll

 ; Check that we fast-isel sret
 %struct.a = type { i64, i64, i64 }
 define void @test20() nounwind ssp {
 entry:
   %tmp = alloca %struct.a, align 8
   call void @test20sret(%struct.a* sret %tmp)
   ret void
 ; CHECK-LABEL: test20:
-; CHECK: leaq (%rsp), %rdi
+; CHECK: movq %rsp, %rdi
 ; CHECK: callq _test20sret
 }
 declare void @test20sret(%struct.a* sret)
 
 ; Check that -0.0 is not materialized using xor
 define void @test21(double* %p1) {
   store double -0.0, double* %p1
   ret void

test/CodeGen/X86/fast-isel-x86.ll

 ; Check that fast-isel sret works with fastcc (and does not callee-pop)
 define void @test4() nounwind ssp {
 entry:
   %tmp = alloca %struct.a, align 8
   call fastcc void @test4fastccsret(%struct.a* sret %tmp)
   ret void
 ; CHECK-LABEL: test4:
 ; CHECK: subl $28
-; CHECK: leal (%esp), %ecx
+; CHECK: movl %esp, %ecx
 ; CHECK: calll _test4fastccsret
 ; CHECK: addl $28
 }
 declare fastcc void @test4fastccsret(%struct.a* sret)
 
 
 ; Check that fast-isel cleans up when it fails to lower a call instruction.
 define void @test5() {

test/CodeGen/X86/frameaddr.ll

 ; CHECK-32:       push
 ; CHECK-32-NEXT:  movl %esp, %ebp
 ; CHECK-32-NEXT:  movl %ebp, %eax
 ; CHECK-32-NEXT:  pop
 ; CHECK-32-NEXT:  ret
 ; CHECK-W64-LABEL: test1
 ; CHECK-W64:       push
 ; CHECK-W64-NEXT:  movq %rsp, %rbp
-; CHECK-W64-NEXT:  leaq (%rbp), %rax
+; CHECK-W64-NEXT:  movq %rbp, %rax
 ; CHECK-W64-NEXT:  pop
 ; CHECK-W64-NEXT:  ret
 ; CHECK-64-LABEL: test1
 ; CHECK-64:       push
 ; CHECK-64-NEXT:  movq %rsp, %rbp
 ; CHECK-64-NEXT:  movq %rbp, %rax
 ; CHECK-64-NEXT:  pop
 ; CHECK-64-NEXT:  ret

 ; CHECK-32-NEXT:  movl %esp, %ebp
 ; CHECK-32-NEXT:  movl (%ebp), %eax
 ; CHECK-32-NEXT:  movl (%eax), %eax
 ; CHECK-32-NEXT:  pop
 ; CHECK-32-NEXT:  ret
 ; CHECK-W64-LABEL: test2
 ; CHECK-W64:       push
 ; CHECK-W64-NEXT:  movq %rsp, %rbp
-; CHECK-W64-NEXT:  leaq (%rbp), %rax
+; CHECK-W64-NEXT:  movq %rbp, %rax
 ; CHECK-W64-NEXT:  pop
 ; CHECK-W64-NEXT:  ret
 ; CHECK-64-LABEL: test2
 ; CHECK-64:       push
 ; CHECK-64-NEXT:  movq %rsp, %rbp
 ; CHECK-64-NEXT:  movq (%rbp), %rax
 ; CHECK-64-NEXT:  movq (%rax), %rax
 ; CHECK-64-NEXT:  pop

test/CodeGen/X86/lea-opt-memop-check-1.ll

define void @test1(i8* nocapture readonly %src, i32 %len) #0 {
   %parts = alloca [4 x i32], align 4
   %part0 = bitcast [4 x i32]* %parts to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %part0, i8* %src, i32 %len, i32 1, i1 false)
   %call0 = tail call <2 x i64> @_mm_xor_si128(<2 x i64> undef, <2 x i64> <i64 -9187201950435737472, i64 -9187201950435737472>)
   %tmp0 = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> undef, <2 x i64> <i64 7631803798, i64 5708721108>, i8 16)
   %call1 = tail call <4 x float> @_mm_castsi128_ps(<2 x i64> %tmp0)
   ret void
 ; CHECK-LABEL: test1:
-; CHECK:  leal{{.*}}
+; CHECK:  movl %esp,
 ; CHECK:  calll _memcpy
 ; CHECK:  movaps __xmm@{{[0-9a-f]+}}, %xmm1
 ; CHECK:  calll __mm_xor_si128
 ; CHECK:  pclmulqdq $16, __xmm@{{[0-9a-f]+}}, %xmm0
 ; CHECK:  jmp __mm_castsi128_ps
 }
 
 declare i32 @GetLastError(...)

test/CodeGen/X86/local_stack_symbol_ordering.ll

 ;   asm ("":::"esi","edi","ebp","ebx","rbx","r12","r13","r14","r15","rbp");
 ;   bar1(&a);
 ; }
 ;
 ; X64: leaq 16(%rsp), %rdi
 ; X64: callq check_a
 ; X64: callq bar1
 ; X64: callq bar1
-; X64: leaq (%rsp), %rdi
+; X64: movq %rsp, %rdi
 ; X64: callq check_f
 ; X64: callq bar1
 ; X64: callq bar3
 ; X64: callq bar2
 ; X64: leaq 12(%rsp), %rdi
 ; X64: callq check_b
 ; X64: callq bar1
 ; X64: callq bar2

test/CodeGen/X86/pr29022.ll

+; RUN: llc < %s -mcpu=skx | not grep -q lea
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define i32 @A() {
+entry:
+  %alloc = alloca i32, align 8
+  %call = call i32 @foo(i32* %alloc)
+  ret i32 %call
+}
+
+declare i32 @foo(i32*)

test/CodeGen/X86/sse-intel-ocl.ll

 ; WIN32: call
 ; WIN32: ret
 
 ; NOT_WIN: testf16_inp
 ; NOT_WIN: addps  {{.*}}, {{%xmm[0-3]}}
 ; NOT_WIN: addps  {{.*}}, {{%xmm[0-3]}}
 ; NOT_WIN: addps  {{.*}}, {{%xmm[0-3]}}
 ; NOT_WIN: addps  {{.*}}, {{%xmm[0-3]}}
-; NOT_WIN: leaq    {{.*}}(%rsp), %rdi
+; NOT_WIN: movq   %rsp, %rdi
 ; NOT_WIN: call
 ; NOT_WIN: ret
 
 ;test calling conventions - input parameters
 define <16 x float> @testf16_inp(<16 x float> %a, <16 x float> %b) nounwind {
   %y = alloca <16 x float>, align 16
   %x = fadd <16 x float> %a, %b
   %1 = call intel_ocl_bicc <16 x float> @func_float16_ptr(<16 x float> %x, <16 x float>* %y) 

test/CodeGen/X86/sse-intrinsics-fast-isel.ll

; X64-NEXT:    retq
   %res = insertelement <4 x float> %a0, float %fdiv, i32 0
   ret <4 x float> %res
 }
 
 define i32 @test_MM_GET_EXCEPTION_MASK() nounwind {
 ; X32-LABEL: test_MM_GET_EXCEPTION_MASK:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:    leal (%esp), %eax
+; X32-NEXT:    movl %esp, %eax
 ; X32-NEXT:    stmxcsr (%eax)
 ; X32-NEXT:    movl (%esp), %eax
 ; X32-NEXT:    andl $8064, %eax # imm = 0x1F80
 ; X32-NEXT:    popl %ecx
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_MM_GET_EXCEPTION_MASK:
 ; X64:       # BB#0:
; X64-NEXT:    retq
   ret i32 %4
 }
 declare void @llvm.x86.sse.stmxcsr(i8*) nounwind readnone
 
 define i32 @test_MM_GET_EXCEPTION_STATE() nounwind {
 ; X32-LABEL: test_MM_GET_EXCEPTION_STATE:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:    leal (%esp), %eax
+; X32-NEXT:    movl %esp, %eax
 ; X32-NEXT:    stmxcsr (%eax)
 ; X32-NEXT:    movl (%esp), %eax
 ; X32-NEXT:    andl $63, %eax
 ; X32-NEXT:    popl %ecx
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_MM_GET_EXCEPTION_STATE:
 ; X64:       # BB#0:
; X64-NEXT:    retq
   %4 = and i32 %3, 63
   ret i32 %4
 }
 
 define i32 @test_MM_GET_FLUSH_ZERO_MODE() nounwind {
 ; X32-LABEL: test_MM_GET_FLUSH_ZERO_MODE:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:    leal (%esp), %eax
+; X32-NEXT:    movl %esp, %eax
 ; X32-NEXT:    stmxcsr (%eax)
 ; X32-NEXT:    movl (%esp), %eax
 ; X32-NEXT:    andl $32768, %eax # imm = 0x8000
 ; X32-NEXT:    popl %ecx
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_MM_GET_FLUSH_ZERO_MODE:
 ; X64:       # BB#0:
; X64-NEXT:    retq
   %4 = and i32 %3, 32768
   ret i32 %4
 }
 
 define i32 @test_MM_GET_ROUNDING_MODE() nounwind {
 ; X32-LABEL: test_MM_GET_ROUNDING_MODE:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:    leal (%esp), %eax
+; X32-NEXT:    movl %esp, %eax
 ; X32-NEXT:    stmxcsr (%eax)
 ; X32-NEXT:    movl (%esp), %eax
 ; X32-NEXT:    andl $24576, %eax # imm = 0x6000
 ; X32-NEXT:    popl %ecx
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_MM_GET_ROUNDING_MODE:
 ; X64:       # BB#0:
; X64-NEXT:    retq
   %4 = and i32 %3, 24576
   ret i32 %4
 }
 
 define i32 @test_mm_getcsr() nounwind {
 ; X32-LABEL: test_mm_getcsr:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
-; X32-NEXT:    leal (%esp), %eax
+; X32-NEXT:    movl %esp, %eax
 ; X32-NEXT:    stmxcsr (%eax)
 ; X32-NEXT:    movl (%esp), %eax
 ; X32-NEXT:    popl %ecx
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_getcsr:
 ; X64:       # BB#0:
 ; X64-NEXT:    leaq -{{[0-9]+}}(%rsp), %rax

 }
 declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
 
 define void @test_MM_SET_EXCEPTION_MASK(i32 %a0) nounwind {
 ; X32-LABEL: test_MM_SET_EXCEPTION_MASK:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    leal (%esp), %ecx
+; X32-NEXT:    movl %esp, %ecx
 ; X32-NEXT:    stmxcsr (%ecx)
 ; X32-NEXT:    movl (%esp), %edx
 ; X32-NEXT:    andl $-8065, %edx # imm = 0xE07F
 ; X32-NEXT:    orl %eax, %edx
 ; X32-NEXT:    movl %edx, (%esp)
 ; X32-NEXT:    ldmxcsr (%ecx)
 ; X32-NEXT:    popl %eax
 ; X32-NEXT:    retl

 }
 declare void @llvm.x86.sse.ldmxcsr(i8*) nounwind readnone
 
 define void @test_MM_SET_EXCEPTION_STATE(i32 %a0) nounwind {
 ; X32-LABEL: test_MM_SET_EXCEPTION_STATE:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    leal (%esp), %ecx
+; X32-NEXT:    movl %esp, %ecx
 ; X32-NEXT:    stmxcsr (%ecx)
 ; X32-NEXT:    movl (%esp), %edx
 ; X32-NEXT:    andl $-64, %edx
 ; X32-NEXT:    orl %eax, %edx
 ; X32-NEXT:    movl %edx, (%esp)
 ; X32-NEXT:    ldmxcsr (%ecx)
 ; X32-NEXT:    popl %eax
 ; X32-NEXT:    retl
; X64-NEXT:    retq
   ret void
 }
 
 define void @test_MM_SET_FLUSH_ZERO_MODE(i32 %a0) nounwind {
 ; X32-LABEL: test_MM_SET_FLUSH_ZERO_MODE:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    leal (%esp), %ecx
+; X32-NEXT:    movl %esp, %ecx
 ; X32-NEXT:    stmxcsr (%ecx)
 ; X32-NEXT:    movl (%esp), %edx
 ; X32-NEXT:    andl $-32769, %edx # imm = 0xFFFF7FFF
 ; X32-NEXT:    orl %eax, %edx
 ; X32-NEXT:    movl %edx, (%esp)
 ; X32-NEXT:    ldmxcsr (%ecx)
 ; X32-NEXT:    popl %eax
 ; X32-NEXT:    retl
; X64-NEXT:    retq
   ret <4 x float> %res3
 }
 
 define void @test_MM_SET_ROUNDING_MODE(i32 %a0) nounwind {
 ; X32-LABEL: test_MM_SET_ROUNDING_MODE:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    leal (%esp), %ecx
+; X32-NEXT:    movl %esp, %ecx
 ; X32-NEXT:    stmxcsr (%ecx)
 ; X32-NEXT:    movl (%esp), %edx
 ; X32-NEXT:    andl $-24577, %edx # imm = 0x9FFF
 ; X32-NEXT:    orl %eax, %edx
 ; X32-NEXT:    movl %edx, (%esp)
 ; X32-NEXT:    ldmxcsr (%ecx)
 ; X32-NEXT:    popl %eax
 ; X32-NEXT:    retl
; X64-NEXT:    retq
   ret <4 x float> %res3
 }
 
 define void @test_mm_setcsr(i32 %a0) nounwind {
 ; X32-LABEL: test_mm_setcsr:
 ; X32:       # BB#0:
 ; X32-NEXT:    pushl %eax
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    leal (%esp), %ecx
+; X32-NEXT:    movl %esp, %ecx
 ; X32-NEXT:    movl %eax, (%esp)
 ; X32-NEXT:    ldmxcsr (%ecx)
 ; X32-NEXT:    popl %eax
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: test_mm_setcsr:
 ; X64:       # BB#0:
 ; X64-NEXT:    leaq -{{[0-9]+}}(%rsp), %rax

test/CodeGen/X86/swift-return.ll

 }
 
 declare swiftcc { i16, i8 } @gen(i32)
 
 ; If we can't pass every return value in register, we will pass everything
 ; in memroy. The caller provides space for the return value and passes
 ; the address in %rax. The first input argument will be in %rdi.
 ; CHECK-LABEL: test2:
-; CHECK: leaq (%rsp), %rax
+; CHECK: movq %rsp, %rax
 ; CHECK: callq gen2
 ; CHECK: movl (%rsp)
 ; CHECK-DAG: addl 4(%rsp)
 ; CHECK-DAG: addl 8(%rsp)
 ; CHECK-DAG: addl 12(%rsp)
 ; CHECK-DAG: addl 16(%rsp)
 ; CHECK-O0-LABEL: test2:
-; CHECK-O0-DAG: leaq (%rsp), %rax
+; CHECK-O0-DAG: movq %rsp, %rax
 ; CHECK-O0: callq gen2
 ; CHECK-O0-DAG: movl (%rsp)
 ; CHECK-O0-DAG: movl 4(%rsp)
 ; CHECK-O0-DAG: movl 8(%rsp)
 ; CHECK-O0-DAG: movl 12(%rsp)
 ; CHECK-O0-DAG: movl 16(%rsp)
 ; CHECK-O0: addl
 ; CHECK-O0: addl

test/CodeGen/X86/win32_sret.ll

 ; CYGWIN-LABEL:     {{^}}_call_foo5:
 ; LINUX-LABEL:      {{^}}call_foo5:
 
 
 ; Load the address of the result and put it onto stack
 ; The this pointer goes to ECX.
 ; (through %ecx in the -O0 build).
 ; WIN32:      leal {{[0-9]*}}(%esp), %e{{[a-d]}}x
-; WIN32:      leal {{[0-9]*}}(%esp), %ecx
+; WIN32:      {{leal [1-9]+\(%esp\)|movl %esp}}, %ecx
 ; WIN32:      {{pushl %e[a-d]x|movl %e[a-d]x, \(%esp\)}}
 ; WIN32-NEXT: calll "?foo@C5@@QAE?AUS5@@XZ"
 ; WIN32:      retl
   ret void
 }
 
 
 %struct.test6 = type { i32, i32, i32 }
 define void @test6_f(%struct.test6* %x) nounwind {
 ; WIN32-LABEL: _test6_f:
 ; MINGW_X86-LABEL: _test6_f:
 ; CYGWIN-LABEL: _test6_f:
 ; LINUX-LABEL: test6_f:
 
 ; The %x argument is moved to %ecx. It will be the this pointer.
 ; WIN32: movl    {{16|20}}(%esp), %ecx
 
 
 ; The sret pointer is (%esp)
-; WIN32:          leal    {{4?}}(%esp), %eax
+; WIN32:      {{leal 4\(%esp\)|movl %esp}}, %eax
 ; WIN32-NEXT:     {{pushl   %eax|movl %eax, \(%esp\)}}
 
 ; The sret pointer is %ecx
 ; The %x argument is moved to (%esp). It will be the this pointer.
-; MINGW_X86:      leal    {{4?}}(%esp), %ecx
+; MINGW_X86:      {{leal 4\(%esp\)|movl %esp}}, %ecx
 ; MINGW_X86-NEXT: {{pushl   16\(%esp\)|movl %eax, \(%esp\)}}
 ; MINGW_X86-NEXT: calll   _test6_g
 
-; CYGWIN:      leal    {{4?}}(%esp), %ecx
+; CYGWIN:      {{leal 4\(%esp\)|movl %esp}}, %ecx
 ; CYGWIN-NEXT: {{pushl   16\(%esp\)|movl %eax, \(%esp\)}}
 ; CYGWIN-NEXT: calll   _test6_g
 
   %tmp = alloca %struct.test6, align 4
   call x86_thiscallcc void @test6_g(%struct.test6* sret %tmp, %struct.test6* %x)
   ret void
 }
 declare x86_thiscallcc void @test6_g(%struct.test6* sret, %struct.test6*)
 
 ; Flipping the parameters at the IR level generates the same code.
 %struct.test7 = type { i32, i32, i32 }
 define void @test7_f(%struct.test7* %x) nounwind {
 ; WIN32-LABEL: _test7_f:
 ; MINGW_X86-LABEL: _test7_f:
 ; CYGWIN-LABEL: _test7_f:
 ; LINUX-LABEL: test7_f:
 
 ; The %x argument is moved to %ecx on all OSs. It will be the this pointer.
 ; WIN32:      movl    {{16|20}}(%esp), %ecx
 ; MINGW_X86:  movl    {{16|20}}(%esp), %ecx
 ; CYGWIN:     movl    {{16|20}}(%esp), %ecx
 
 ; The sret pointer is (%esp)
-; WIN32:          leal    {{4?}}(%esp), %eax
+; WIN32:      {{leal 4\(%esp\)|movl %esp}}, %eax
 ; WIN32-NEXT:     {{pushl   %eax|movl %eax, \(%esp\)}}
-; MINGW_X86:      leal    {{4?}}(%esp), %eax
+; MINGW_X86:      {{leal 4\(%esp\)|movl %esp}}, %eax
 ; MINGW_X86-NEXT: {{pushl   %eax|movl %eax, \(%esp\)}}
-; CYGWIN:         leal    {{4?}}(%esp), %eax
+; CYGWIN:      {{leal 4\(%esp\)|movl %esp}}, %eax
 ; CYGWIN-NEXT: {{pushl   %eax|movl %eax, \(%esp\)}}
 
   %tmp = alloca %struct.test7, align 4
   call x86_thiscallcc void @test7_g(%struct.test7* %x, %struct.test7* sret %tmp)
   ret void
 }
 
 define x86_thiscallcc void @test7_g(%struct.test7* %in, %struct.test7* sret %out) {

test/CodeGen/X86/win64_frame.ll

define i32 @f8(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) "no-frame-pointer-elim"="true" {
   ; CHECK:        movabsq $34359738352, %rax
   ; CHECK:        andq    %rcx, %rax
   ; CHECK:        callq   __chkstk
   ; CHECK:        subq    %rax, %rsp
 
   %gep = getelementptr [300 x i8], [300 x i8]* %alloca, i32 0, i32 0
   call void @external(i8* %gep)
   ; CHECK:        subq    $32, %rsp
-  ; CHECK:        leaq    (%rbx), %rcx
+  ; CHECK:        movq    %rbx, %rcx
   ; CHECK:        callq   external
   ; CHECK:        addq    $32, %rsp
 
   ret i32 %e
   ; CHECK:        movl    %esi, %eax
   ; CHECK:        leaq    224(%rbp), %rsp
 }
 

test/DebugInfo/COFF/inlining.ll

 ; OBJ:   }
 ; OBJ: ]
 ; OBJ: Subsection [
 ; OBJ:   SubSectionType: Symbols (0xF1)
 ; OBJ:   ProcStart {
 ; OBJ:     PtrParent: 0x0
 ; OBJ:     PtrEnd: 0x0
 ; OBJ:     PtrNext: 0x0
-; OBJ:     CodeSize: 0x3D
+; OBJ:     CodeSize: 0x3C
 ; OBJ:     DbgStart: 0x0
 ; OBJ:     DbgEnd: 0x0
 ; OBJ:     FunctionType: baz (0x1004)
 ; OBJ:     CodeOffset: ?baz@@YAXXZ+0x0
 ; OBJ:     Segment: 0x0
 ; OBJ:     Flags [ (0x0)
 ; OBJ:     ]
 ; OBJ:     DisplayName: baz
 ; OBJ:     LinkageName: ?baz@@YAXXZ
 ; OBJ:   }
 ; OBJ:   InlineSite {
 ; OBJ:     PtrParent: 0x0
 ; OBJ:     PtrEnd: 0x0
 ; OBJ:     Inlinee: bar (0x1002)
 ; OBJ:      BinaryAnnotations [
 ; OBJ-NEXT:   ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x8, LineOffset: 1}
 ; OBJ-NEXT:   ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x7, LineOffset: 1}
 ; OBJ-NEXT:   ChangeLineOffset: 1
-; OBJ-NEXT:   ChangeCodeOffset: 0x1E
+; OBJ-NEXT:   ChangeCodeOffset: 0x1D
 ; OBJ-NEXT:   ChangeCodeLength: 0x7
 ; OBJ:      ]
 ; OBJ:   }
 ; OBJ:   InlineSite {
 ; OBJ:     PtrParent: 0x0
 ; OBJ:     PtrEnd: 0x0
 ; OBJ:     Inlinee: foo (0x1003)
 ; OBJ:     BinaryAnnotations [
 ; OBJ-NEXT:  ChangeCodeOffsetAndLineOffset: {CodeOffset: 0xF, LineOffset: 1}
-; OBJ-NEXT:  ChangeCodeOffsetAndLineOffset: {CodeOffset: 0xA, LineOffset: 1}
+; OBJ-NEXT:  ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x9, LineOffset: 1}
 ; OBJ-NEXT:  ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x6, LineOffset: 1}
 ; OBJ-NEXT:  ChangeCodeOffsetAndLineOffset: {CodeOffset: 0x7, LineOffset: 1}
 ; OBJ-NEXT:  ChangeCodeLength: 0x7
 ; OBJ:     ]
 ; OBJ:   }
 ; OBJ:   InlineSiteEnd {
 ; OBJ:   }
 ; OBJ:   InlineSiteEnd {