Synchronize the NaCl DataLayout string with the one in clang

[• rafael]

Summary

Derek tells me they have local changes for DataLayout for NaCl.

This patch simply synchronizes llvm so that it produces the same string as clang. Once clang is using the llvm strings it should be easy to upstream the changes.

[dschuff]

Thanks for looking at this.
Just to refresh my memory, the preferred alignment defaults to the ABI alignment, so e.g. i64:64:64 is equivalent to i64:64, correct?

lib/Target/ARM/ARMTargetMachine.cpp

93

NaCl uses AAPCS VFP conventions, with a stack alignment of 16 bytes. Would it make more sense just to set that in ARMSubtarget.cpp instead of special casing here?

lib/Target/X86/X86TargetMachine.cpp

43

I'm a little unclear about this; does this mean 64-bit targets have i64 but not f64?
NaCl does use f64:64 and i64:64 for both 32 and 64 bits, but I don't see where else but here that f64 is even set.

56

This can be removed. Clang seems to have it it upstream, but that's wrong. vectors are never generated for le32, and for i686-nacl and x86_64-nacl they have the same alignment as linux.

59

I think this condition can move to just the stack alignment, as we use s32-n8:16:32-S128 for i686-nacl and s:64-n8:16:32:64-S128 for x86_64-nacl

[• rafael]

Updated with the new strings in clang.

[dschuff]

LGTM, thanks!

[• rafael]

Committed as r197640.

[jfb]

lib/Target/X86/X86TargetMachine.cpp

50

I'm editing this line in D5807.

lib/Target/ARM/ARMTargetMachine.cpp

static std::string computeDataLayout(ARMSubtarget &ST) {
 
   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
   // bits, others to 64 bits. We always try to align to 64 bits.
   if (ST.isAPCS_ABI())
     Ret += "-f64:32:64";
 
   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
   // to 64. We always ty to give them natural alignment.
-  if (ST.isAPCS_ABI())
+  if (ST.isTargetNaCl())
+    Ret += "-v128:32";
+  else if (ST.isAPCS_ABI())
     Ret += "-v64:32:64-v128:32:128";
   else
     Ret += "-v128:64:128";
 
   // On thumb and APCS, only try to align aggregates to 32 bits (the default is
   // 64 bits).
   if (ST.isThumb() || ST.isAPCS_ABI())
     Ret += "-a:0:32";
 
+  if (!ST.isTargetNaCl()) {
     // Integer registers are 32 bits.
     Ret += "-n32";
 
     // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
     if (ST.isAAPCS_ABI())
       Ret += "-S64";
     else
       Ret += "-S32";
+  }
 
   return Ret;
 }
 
 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
                                    Reloc::Model RM, CodeModel::Model CM,

lib/Target/X86/X86Subtarget.h

 public:
   /// Is this x86_64? (disregarding specific ABI / programming model)
   bool is64Bit() const {
     return In64BitMode;
   }
 
   /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
   bool isTarget64BitILP32() const {
-    return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32);
+    return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
+                           TargetTriple.getOS() == Triple::NaCl);
   }
 
   /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
   bool isTarget64BitLP64() const {
     return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32);
   }
 
   PICStyles::Style getPICStyle() const { return PICStyle; }

lib/Target/X86/X86TargetMachine.cpp

static std::string computeDataLayout(const X86Subtarget &ST) {
   // X86 is little endian
   std::string Ret = "e";
 
   // X86 and x32 have 32 bit pointers.
   if (ST.isTarget64BitILP32() || !ST.is64Bit())
     Ret += "-p:32:32";
 
   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
-  if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows())
+  if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows() ||
+      ST.isTargetNaCl())
     Ret += "-i64:64";
   else
     Ret += "-f64:32:64";
 
   // Some ABIs align long double to 128 bits, others to 32.
-  if (ST.is64Bit() || ST.isTargetDarwin())
+  if (ST.isTargetNaCl())
+    ; // No f80
+  else if (ST.is64Bit() || ST.isTargetDarwin())
     Ret += "-f80:128";
   else
     Ret += "-f80:32";
 
+  if (ST.isTargetNaCl())
+    Ret += "-v128:32";
+
+  if (!ST.isTargetNaCl()) {
     // Objects on the stack ore aligned to 64 bits.
     if (ST.is64Bit())
       Ret += "-s:64";
 
     // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
     if (ST.is64Bit())
       Ret += "-n8:16:32:64";
     else
       Ret += "-n8:16:32";
 
     // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
     if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetWindows()))
       Ret += "-S32";
     else
       Ret += "-S128";
+  }
 
   return Ret;
 }
 
 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
                                          StringRef CPU, StringRef FS,
                                          const TargetOptions &Options,
                                          Reloc::Model RM, CodeModel::Model CM,