Don't reduce mul if the target doesn't support SSE2

[wmi]

Summary

The patch is to fix https://llvm.org/bugs/show_bug.cgi?id=30298, which is caused by https://reviews.llvm.org/D20931

pmullw/pmulhw/punpcklwd/punpckhwd are not supported in SSE, so I add a bail out if the target has no SSE2.

[mkuper]

Thanks, Wei.
The change LGTM, but can you fix the test up a bit?

test/CodeGen/X86/pr30298.ll

1 ↗

(On Diff #70499)

I don't see why this test would require asserts. A copy/paste bug?

3 ↗

(On Diff #70499)

Please add a positive check for the code we do expect.

[wmi]

test/CodeGen/X86/pr30298.ll

1 ↗

(On Diff #70499)

It doesn't need it. I do want the test to be effective even if the test doesn't enable assertion. And I think that is why you suggest me to give a positive check. Thanks!

3 ↗

(On Diff #70499)

Ok. will add it.

[wmi]

Address Michael's comments.

[mkuper]

LGTM, except another small change to the test.
(No need to reupload the changed version for review, feel free to commit)

test/CodeGen/X86/pr30298.ll

6 ↗

(On Diff #70554)

Can you mark the function nounwind, so that that we don't have all the cfi clutter?

[wmi]

test/CodeGen/X86/pr30298.ll

6 ↗

(On Diff #70554)

I was thinking how to remove the cfi directives but didn't a way to achieve it. Gcc option -fno-dwarf2-cfi-asm doesn't work for llvm.

Thanks a lot for the idea.

[dim]

FWIW, for me it fixes both the original test case (from libx264), and the reduced test case from PR 30298. Thanks. :)

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

 /// generate pmullw+pmulhw for it (MULS16 mode).
 /// If %2 == zext32(trunc16(%2)), i.e., the scalar value range of %2 is
 /// 0 to 65535, and the scalar value range of %4 is also 0 to 65535,
 /// generate pmullw+pmulhuw for it (MULU16 mode).
 static SDValue reduceVMULWidth(SDNode *N, SelectionDAG &DAG,
                                const X86Subtarget &Subtarget) {
   // pmulld is supported since SSE41. It is better to use pmulld
   // instead of pmullw+pmulhw.
-  if (Subtarget.hasSSE41())
+  // pmullw/pmulhw are not supported by SSE.
+  if (Subtarget.hasSSE41() || !Subtarget.hasSSE2())
     return SDValue();
 
   ShrinkMode Mode;
   if (!canReduceVMulWidth(N, DAG, Mode))
     return SDValue();
 
   SDLoc DL(N);
   SDValue N0 = N->getOperand(0);

llvm/trunk/test/CodeGen/X86/pr30298.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=i386-pc-linux-gnu -mattr=+sse < %s | FileCheck %s
+
+@c = external global i32*, align 8
+
+define void @mul_2xi8(i8* nocapture readonly %a, i8* nocapture readonly %b, i64 %index) nounwind {
+; CHECK-LABEL: mul_2xi8:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    pushl %ebx
+; CHECK-NEXT:    pushl %edi
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT:    movl c, %esi
+; CHECK-NEXT:    movzbl 1(%edx,%ecx), %edi
+; CHECK-NEXT:    movzbl (%edx,%ecx), %edx
+; CHECK-NEXT:    movzbl 1(%eax,%ecx), %ebx
+; CHECK-NEXT:    movzbl (%eax,%ecx), %eax
+; CHECK-NEXT:    imull %edx, %eax
+; CHECK-NEXT:    imull %edi, %ebx
+; CHECK-NEXT:    movl %ebx, 4(%esi,%ecx,4)
+; CHECK-NEXT:    movl %eax, (%esi,%ecx,4)
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    popl %edi
+; CHECK-NEXT:    popl %ebx
+; CHECK-NEXT:    retl
+entry:
+  %pre = load i32*, i32** @c
+  %tmp6 = getelementptr inbounds i8, i8* %a, i64 %index
+  %tmp7 = bitcast i8* %tmp6 to <2 x i8>*
+  %wide.load = load <2 x i8>, <2 x i8>* %tmp7, align 1
+  %tmp8 = zext <2 x i8> %wide.load to <2 x i32>
+  %tmp10 = getelementptr inbounds i8, i8* %b, i64 %index
+  %tmp11 = bitcast i8* %tmp10 to <2 x i8>*
+  %wide.load17 = load <2 x i8>, <2 x i8>* %tmp11, align 1
+  %tmp12 = zext <2 x i8> %wide.load17 to <2 x i32>
+  %tmp13 = mul nuw nsw <2 x i32> %tmp12, %tmp8
+  %tmp14 = getelementptr inbounds i32, i32* %pre, i64 %index
+  %tmp15 = bitcast i32* %tmp14 to <2 x i32>*
+  store <2 x i32> %tmp13, <2 x i32>* %tmp15, align 4
+  ret void
+}