[mips] Disable the TImode shift libcalls for 32-bit targets.

[vkalintiris]

Summary

The o32 ABI doesn't not support the TImode helpers. For the time being,
disable just the shift libcalls as they break recursive builds on MIPS.

[sdardis]

LGTM.

llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
   setTargetDAGCombine(ISD::SDIVREM);
   setTargetDAGCombine(ISD::UDIVREM);
   setTargetDAGCombine(ISD::SELECT);
   setTargetDAGCombine(ISD::AND);
   setTargetDAGCombine(ISD::OR);
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::AssertZext);
 
+  if (ABI.IsO32()) {
+    // These libcalls are not available in 32-bit.
+    setLibcallName(RTLIB::SHL_I128, nullptr);
+    setLibcallName(RTLIB::SRL_I128, nullptr);
+    setLibcallName(RTLIB::SRA_I128, nullptr);
+  }
+
   setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
 
   // The arguments on the stack are defined in terms of 4-byte slots on O32
   // and 8-byte slots on N32/N64.
   setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
 
   setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll

; ALL-LABEL: ashr_i64:
   %r = ashr i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i128:
 
-  ; GP32:           lw        $25, %call16(__ashrti3)($gp)
+  ; o32 shouldn't use TImode helpers.
+  ; GP32-NOT:       lw        $25, %call16(__ashrti3)($gp)
+  ; MM-NOT:         lw        $25, %call16(__ashrti3)($2)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrav     $[[T1:[0-9]+]], $4, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], [[BB0:.LBB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
   ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $7
   ; M3:             dsll      $[[T5:[0-9]+]], $4, 1
; ALL-LABEL: ashr_i128:
   ; 64R6:           not       $[[T9:[0-9]+]], $[[T1]]
   ; 64R6:           dsllv     $[[T10:[0-9]+]], $[[T8]], $[[T9]]
   ; 64R6:           or        $[[T11:[0-9]+]], $[[T10]], $[[T7]]
   ; 64R6:           seleqz    $[[T12:[0-9]+]], $[[T11]], $[[T3]]
   ; 64R6:           selnez    $[[T13:[0-9]+]], $[[T0]], $[[T3]]
   ; 64R6:           jr        $ra
   ; 64R6:           or        $3, $[[T13]], $[[T12]]
 
-  ; MM:             lw        $25, %call16(__ashrti3)($2)
-
   %r = ashr i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll

; ALL-LABEL: lshr_i64:
   %r = lshr i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: lshr_i128:
 
-  ; GP32:         lw      $25, %call16(__lshrti3)($gp)
+  ; o32 shouldn't use TImode helpers.
+  ; GP32-NOT:       lw        $25, %call16(__lshrti3)($gp)
+  ; MM-NOT:         lw        $25, %call16(__lshrti3)($2)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsrlv     $[[T1:[0-9]+]], $4, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]]
   ; M3:             move      $3, $[[T1]]
   ; M3:             dsrlv     $[[T4:[0-9]+]], $5, $7
   ; M3:             dsll      $[[T5:[0-9]+]], $4, 1
; ALL-LABEL: lshr_i128:
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
   ; 64R6:           dsrlv     $[[T9:[0-9]+]], $4, $7
   ; 64R6:           selnez    $[[T10:[0-9]+]], $[[T9]], $[[T7]]
   ; 64R6:           or        $3, $[[T10]], $[[T8]]
   ; 64R6:           jr        $ra
   ; 64R6:           seleqz    $2, $[[T9]], $[[T7]]
 
-  ; MM:             lw        $25, %call16(__lshrti3)($2)
-
   %r = lshr i128 %a, %b
   ret i128 %r
 }

llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll

; ALL-LABEL: shl_i64:
   %r = shl i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: shl_i128:
 
-  ; GP32:           lw        $25, %call16(__ashlti3)($gp)
+  ; o32 shouldn't use TImode helpers.
+  ; GP32-NOT:       lw        $25, %call16(__ashlti3)($gp)
+  ; MM-NOT:         lw        $25, %call16(__ashlti3)($2)
 
   ; M3:             sll       $[[T0:[0-9]+]], $7, 0
   ; M3:             dsllv     $[[T1:[0-9]+]], $5, $7
   ; M3:             andi      $[[T2:[0-9]+]], $[[T0]], 64
   ; M3:             bnez      $[[T3:[0-9]+]], [[BB0:\.LBB[0-9_]+]]
   ; M3:             move      $2, $[[T1]]
   ; M3:             dsllv     $[[T4:[0-9]+]], $4, $7
   ; M3:             dsrl      $[[T5:[0-9]+]], $5, 1
; ALL-LABEL: shl_i128:
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
   ; 64R6:           dsllv     $[[T9:[0-9]+]], $5, $7
   ; 64R6:           selnez    $[[T10:[0-9]+]], $[[T9]], $[[T7]]
   ; 64R6:           or        $2, $[[T10]], $[[T8]]
   ; 64R6:           jr        $ra
   ; 64R6:           seleqz    $3, $[[T9]], $[[T7]]
 
-  ; MM:             lw        $25, %call16(__ashlti3)($2)
-
   %r = shl i128 %a, %b
   ret i128 %r
 }