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Differential D24016

AMDGPU: Relax SGPR asm constraint register class
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Authored by arsenm on Aug 29 2016, 5:34 PM.

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• tstellarAMD

Summary

s should be SReg_32 to be as general as possible. This can avoid a copy from m0.

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arsenm updated this revision to Diff 69638.Aug 29 2016, 5:34 PM

arsenm retitled this revision from to AMDGPU: Relax SGPR asm constraint register class.

arsenm updated this object.

arsenm added a reviewer: • tstellarAMD.

arsenm added a subscriber: llvm-commits.

Herald added subscribers: wdng, arsenm. · View Herald TranscriptAug 29 2016, 5:34 PM

LGTM.

This revision is now accepted and ready to land.Aug 30 2016, 7:26 AM

r280154

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

SIISelLowering.cpp

2 lines

test/

CodeGen/

AMDGPU/

inline-constraints.ll

10 lines

Diff 69638

lib/Target/AMDGPU/SIISelLowering.cpp

Show First 20 Lines • Show All 3,745 Lines • ▼ Show 20 Lines	SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (Constraint.size() == 1) {		if (Constraint.size() == 1) {
switch (Constraint[0]) {		switch (Constraint[0]) {
case 's':		case 's':
case 'r':		case 'r':
switch (VT.getSizeInBits()) {		switch (VT.getSizeInBits()) {
default:		default:
return std::make_pair(0U, nullptr);		return std::make_pair(0U, nullptr);
case 32:		case 32:
return std::make_pair(0U, &AMDGPU::SGPR_32RegClass);		return std::make_pair(0U, &AMDGPU::SReg_32RegClass);
case 64:		case 64:
return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);		return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
case 128:		case 128:
return std::make_pair(0U, &AMDGPU::SReg_128RegClass);		return std::make_pair(0U, &AMDGPU::SReg_128RegClass);
case 256:		case 256:
return std::make_pair(0U, &AMDGPU::SReg_256RegClass);		return std::make_pair(0U, &AMDGPU::SReg_256RegClass);
}		}

▲ Show 20 Lines • Show All 50 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/inline-constraints.ll

Show All 15 Lines	entry:
%v64 = tail call <2 x i32> asm sideeffect "flat_load_dwordx2 $0, $1", "=v,v"(i32 addrspace(1)* %ptr)		%v64 = tail call <2 x i32> asm sideeffect "flat_load_dwordx2 $0, $1", "=v,v"(i32 addrspace(1)* %ptr)
%v128 = tail call <4 x i32> asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(i32 addrspace(1)* %ptr)		%v128 = tail call <4 x i32> asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(i32 addrspace(1)* %ptr)
%s32 = tail call i32 asm sideeffect "s_load_dword $0, $1", "=s,s"(i32 addrspace(1)* %ptr)		%s32 = tail call i32 asm sideeffect "s_load_dword $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
%s64 = tail call <2 x i32> asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)		%s64 = tail call <2 x i32> asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
%s128 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)		%s128 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
%s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)		%s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
ret void		ret void
}		}

		; GCN-LABEL: {{^}}inline_sreg_constraint_m0:
		; GCN: s_mov_b32 m0, -1
		; GCN-NOT: s_mov_b32 s{{[0-9]+}}, m0
		; GCN: ; use m0
		define void @inline_sreg_constraint_m0(i32 addrspace(1)* %ptr) {
		%m0 = tail call i32 asm sideeffect "s_mov_b32 m0, -1", "={M0}"()
		tail call void asm sideeffect "; use $0", "s"(i32 %m0)
		ret void
		}