[AArch64 NEON] Add patterns for loading vector constant from constant poll.

[kevin.qin]

Summary

Hi,

In AArch64, most of loading constant from constant poll are implemented as:

adrp x0, .Label
ld x1, [x0, #.lo12.Label]

But for vector load LD1, it doesn't have pre-index format. So I have to choose one of the sequence below:

adrp x0, .Label
add x0, x0, #.lo12.Label
ld1 {x1}, [x0]

adr x0, .Label
ld1 {x1}, [x0]

I'm not quite familiar with ADRP and ADR, so I simply choose the second one as it has less instruction.
Please review, thanks.

[t.p.northover]

Hi Kevin,

A single ADR is incorrect. The constants are in a separate section, which means they might be up to 4GB away from the code executing. It's no coincidence that this is precisely the distance an ADRP/ADD pair is capable of addressing (ADR can only do 2MB, I think).

That said, there's no particular reason for these to be NEON loads. On little-endian machines "ldr qD, [xN, :lo12:whatever]" (or "dD") does the same thing, and on big-endian machines (if anyone ever cares enough) we can change the constpool entry so that it still works. That's probably the most efficient way to handle it.

Cheers.

Tim

[kevin.qin]

Use LDR instead. Please reivew. Thanks.

[t.p.northover]

Hi Kevin,

Thanks for the updated version. It looks good, but reveals a couple more changes that should go in at the same time:

lib/Target/AArch64/AArch64ISelLowering.cpp

2275–2277 ↗

(On Diff #6122)

This means that the corresponding case in AArch64ISelDAGToDAG.cpp:1116 will never trigger. That's a *very* good thing, since your version is actually correct (I've no idea what I was thinking when I wrote that) but it should probably be removed.

Could you also modify the neon-mov.ll test to make sure this doesn't happen again (from current codegen, but should be fixed with your patch):

movi1d:                                 // @movi1d
    .cfi_startproc
    ldr	d0, [.LCPI40_0, #0]    // WTF???
    movi	 d1, #0xffffffff0000
    b	test_movi1d

[kevin.qin]

Hi Tim,

Thanks for your review. Some changes on AArch64ISelDAGToDAG and neon-mov.ll followed your comments.

[t.p.northover]

Looks good to me. Thanks for working on the revisions.

Cheers.

Tim.

[Eugene.Zelenko]

Committed in rL197551.

lib/Target/AArch64/AArch64InstrNEON.td

 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
 
+def : Pat<(v2f64 (load constpool:$label)),
+          (LD1_2D (ADRxi $label))>;
+def : Pat<(v2i64 (load constpool:$label)),
+          (LD1_2D (ADRxi $label))>;
+
+def : Pat<(v4f32 (load constpool:$label)),
+          (LD1_4S (ADRxi $label))>;
+def : Pat<(v4i32 (load constpool:$label)),
+          (LD1_4S (ADRxi $label))>;
+
+def : Pat<(v8i16 (load constpool:$label)),
+          (LD1_8H (ADRxi $label))>;
+def : Pat<(v16i8 (load constpool:$label)),
+          (LD1_16B (ADRxi $label))>;
+
+def : Pat<(v1f64 (load constpool:$label)),
+          (LD1_1D (ADRxi $label))>;
+def : Pat<(v1i64 (load constpool:$label)),
+          (LD1_1D (ADRxi $label))>;
+
+def : Pat<(v2i32 (load constpool:$label)),
+          (LD1_2S (ADRxi $label))>;
+def : Pat<(v2f32 (load constpool:$label)),
+          (LD1_2S (ADRxi $label))>;
+
+def : Pat<(v4i16 (load constpool:$label)),
+          (LD1_4H (ADRxi $label))>;
+def : Pat<(v8i8 (load constpool:$label)),
+          (LD1_8B (ADRxi $label))>;
+
 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),

test/CodeGen/AArch64/neon-simd-ldst-one.ll

   ret void
 }
 
+define <16 x i8> @test_ld_from_poll_v16i8(<16 x i8> %a) {
+; CHECK-LABEL: test_ld_from_poll_v16i8
+; CHECK: adr {{x[0-9]+}}, .{{[A-Z0-9_]+}}
+; CHECK-NEXT: ld1 {{{v[0-9]+}}.16b}, [{{x[0-9]+}}]
+entry:
+  %b = add <16 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>
+  ret <16 x i8> %b
+}
+
+define <8 x i16> @test_ld_from_poll_v8i16(<8 x i16> %a) {
+; CHECK-LABEL: test_ld_from_poll_v8i16
+; CHECK: adr {{x[0-9]+}}, .{{[A-Z0-9_]+}}
+; CHECK-NEXT: ld1 {{{v[0-9]+}}.8h}, [{{x[0-9]+}}]
+entry:
+  %b = add <8 x i16> %a, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
+  ret <8 x i16> %b
+}
+
+define <4 x i32> @test_ld_from_poll_v4i32(<4 x i32> %a) {
+; CHECK-LABEL: test_ld_from_poll_v4i32
+; CHECK: adr {{x[0-9]+}}, .{{[A-Z0-9_]+}}
+; CHECK-NEXT: ld1 {{{v[0-9]+}}.4s}, [{{x[0-9]+}}]
+entry:
+  %b = add <4 x i32> %a, <i32 1, i32 2, i32 3, i32 4>
+  ret <4 x i32> %b
+}
+
+define <2 x i64> @test_ld_from_poll_v2i64(<2 x i64> %a) {
+; CHECK-LABEL: test_ld_from_poll_v2i64
+; CHECK: adr {{x[0-9]+}}, .{{[A-Z0-9_]+}}
+; CHECK-NEXT: ld1 {{{v[0-9]+}}.2d}, [{{x[0-9]+}}]
+entry:
+  %b = add <2 x i64> %a, <i64 1, i64 2>
+  ret <2 x i64> %b
+}
+
+define <8 x i8> @test_ld_from_poll_v8i8(<8 x i8> %a) {
+; CHECK-LABEL: test_ld_from_poll_v8i8
+; CHECK: adr {{x[0-9]+}}, .{{[A-Z0-9_]+}}
+; CHECK-NEXT: ld1 {{{v[0-9]+}}.8b}, [{{x[0-9]+}}]
+entry:
+  %b = add <8 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
+  ret <8 x i8> %b
+}
+
+define <4 x i16> @test_ld_from_poll_v4i16(<4 x i16> %a) {
+; CHECK-LABEL: test_ld_from_poll_v4i16
+; CHECK: adr {{x[0-9]+}}, .{{[A-Z0-9_]+}}
+; CHECK-NEXT: ld1 {{{v[0-9]+}}.4h}, [{{x[0-9]+}}]
+entry:
+  %b = add <4 x i16> %a, <i16 1, i16 2, i16 3, i16 4>
+  ret <4 x i16> %b
+}
+
+define <2 x i32> @test_ld_from_poll_v2i32(<2 x i32> %a) {
+; CHECK-LABEL: test_ld_from_poll_v2i32
+; CHECK: adr {{x[0-9]+}}, .{{[A-Z0-9_]+}}
+; CHECK-NEXT: ld1 {{{v[0-9]+}}.2s}, [{{x[0-9]+}}]
+entry:
+  %b = add <2 x i32> %a, <i32 1, i32 2>
+  ret <2 x i32> %b
+}
+
+define <4 x float> @test_ld_from_poll_v4f32(<4 x float> %a) {
+; CHECK-LABEL: test_ld_from_poll_v4f32
+; CHECK: adr {{x[0-9]+}}, .{{[A-Z0-9_]+}}
+; CHECK-NEXT: ld1 {{{v[0-9]+}}.4s}, [{{x[0-9]+}}]
+entry:
+  %b = fadd <4 x float> %a, <float 1.0, float 2.0, float 3.0, float 4.0>
+  ret <4 x float> %b
+}
+
+define <2 x double> @test_ld_from_poll_v2f64(<2 x double> %a) {
+; CHECK-LABEL: test_ld_from_poll_v2f64
+; CHECK: adr {{x[0-9]+}}, .{{[A-Z0-9_]+}}
+; CHECK-NEXT: ld1 {{{v[0-9]+}}.2d}, [{{x[0-9]+}}]
+entry:
+  %b = fadd <2 x double> %a, <double 1.0, double 2.0>
+  ret <2 x double> %b
+}
+
 declare { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2lane.v16i8(i8*, <16 x i8>, <16 x i8>, i32, i32)
 declare { <8 x i16>, <8 x i16> } @llvm.arm.neon.vld2lane.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32)
 declare { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32)