MachineScheduler: Make some GenericScheduler member variables protected

[• tstellarAMD]

Summary

We will need these in AMDGPU's new SchedStrategy implmentation.

[MatzeB]

LGTM.

[atrick]

Whatever works for you. I was thinking custom schedulers would use composition of utilities rather than inheriting the whole set of heuristics. It comes down to whether you want someone tuning the GenericScheduler to impact performance on your target. They will have no way to evaluate it.

[• tstellarAMD]

In D23679#520360, @atrick wrote:

Whatever works for you. I was thinking custom schedulers would use composition of utilities rather than inheriting the whole set of heuristics. It comes down to whether you want someone tuning the GenericScheduler to impact performance on your target. They will have no way to evaluate it.

The custom heuristics are working well for us so far, I just needed a way to have better control over the register pressure limits.

llvm/trunk/include/llvm/CodeGen/MachineScheduler.h

 #ifndef NDEBUG
   void traceCandidate(const SchedCandidate &Cand);
 #endif
 };
 
 /// GenericScheduler shrinks the unscheduled zone using heuristics to balance
 /// the schedule.
 class GenericScheduler : public GenericSchedulerBase {
-  ScheduleDAGMILive *DAG;
-
-  // State of the top and bottom scheduled instruction boundaries.
-  SchedBoundary Top;
-  SchedBoundary Bot;
-
-  /// Candidate last picked from Top boundary.
-  SchedCandidate TopCand;
-  /// Candidate last picked from Bot boundary.
-  SchedCandidate BotCand;
-
-  MachineSchedPolicy RegionPolicy;
 public:
   GenericScheduler(const MachineSchedContext *C):
     GenericSchedulerBase(C), DAG(nullptr), Top(SchedBoundary::TopQID, "TopQ"),
     Bot(SchedBoundary::BotQID, "BotQ") {}
 
   void initPolicy(MachineBasicBlock::iterator Begin,
                   MachineBasicBlock::iterator End,
                   unsigned NumRegionInstrs) override;
public:
   void releaseBottomNode(SUnit *SU) override {
     Bot.releaseBottomNode(SU);
     BotCand.SU = nullptr;
   }
 
   void registerRoots() override;
 
 protected:
+  ScheduleDAGMILive *DAG;
+
+  MachineSchedPolicy RegionPolicy;
+
+  // State of the top and bottom scheduled instruction boundaries.
+  SchedBoundary Top;
+  SchedBoundary Bot;
+
+  /// Candidate last picked from Top boundary.
+  SchedCandidate TopCand;
+  /// Candidate last picked from Bot boundary.
+  SchedCandidate BotCand;
+
+
   void checkAcyclicLatency();
 
   void initCandidate(SchedCandidate &Cand, SUnit *SU, bool AtTop,
                      const RegPressureTracker &RPTracker,
                      RegPressureTracker &TempTracker);
 
   void tryCandidate(SchedCandidate &Cand,
                     SchedCandidate &TryCand,