[mips][fastisel] Handle 0-4 arguments without SelectionDAG.

[dsanders]

Summary

Implements fastLowerArguments() to avoid the need to fall back on
SelectionDAG for 0-4 argument functions that don't do tricky things like
passing double in a pair of i32's.

This allows us to move all except one test to -fast-isel-abort=3. The
remaining one has function prototypes of the form 'i32 (i32, double, double)'
which requires floats to be passed in GPR's.

[sdardis]

LTGM though callabi.ll (functions cxcccc & cxhhhh) has some extra changes with my local copy of LLVM. It appears there's another frame object object being allocated which changes the offsets. Ok with that test fixed.

lib/Target/Mips/MipsFastISel.cpp

1272

".. gave up (calling convention is not C)" is clearer here I think.

test/CodeGen/Mips/Fast-ISel/callabi.ll

186–190

Stack slot has a 24 byte offset.

221–225

Stack slot has 24 byte offset here as well.

[dsanders]

lib/Target/Mips/MipsFastISel.cpp

1272

I unintentionally committed before fixing this so I made this change in r276984

test/CodeGen/Mips/Fast-ISel/callabi.ll

186–190

It was 16 when I ran 'ninja check' just before the commit so I haven't made this change.

221–225

It was 16 when I ran 'ninja check' just before the commit so I haven't made this change.

lib/Target/Mips/MipsFastISel.cpp

 #include "llvm/CodeGen/FunctionLoweringInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/IR/GetElementPtrTypeIterator.h"
 #include "llvm/IR/GlobalAlias.h"
 #include "llvm/IR/GlobalVariable.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "mips-fastisel"
 
 using namespace llvm;
 
 namespace {
 
 class MipsFastISel final : public FastISel {
 
   // All possible address modes.
class MipsFastISel final : public FastISel {
   const MipsSubtarget *Subtarget;
   const TargetInstrInfo &TII;
   const TargetLowering &TLI;
   MipsFunctionInfo *MFI;
 
   // Convenience variables to avoid some queries.
   LLVMContext *Context;
 
+  bool fastLowerArguments() override;
   bool fastLowerCall(CallLoweringInfo &CLI) override;
   bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
 
   bool TargetSupported;
   bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
   // floating point but not reject doing fast-isel in other
   // situations
 
if (RetVT != MVT::isVoid) {
     CLI.InRegs.push_back(RVLocs[0].getLocReg());
 
     CLI.ResultReg = ResultReg;
     CLI.NumResultRegs = 1;
   }
   return true;
 }
 
+bool MipsFastISel::fastLowerArguments() {
+  DEBUG(dbgs() << "fastLowerArguments\n");
+
+  if (!FuncInfo.CanLowerReturn) {
+    DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
+    return false;
+  }
+
+  const Function *F = FuncInfo.Fn;
+  if (F->isVarArg()) {
+    DEBUG(dbgs() << ".. gave up (varargs)\n");
+    return false;
+  }
+
+  CallingConv::ID CC = F->getCallingConv();
+  if (CC != CallingConv::C) {
+    DEBUG(dbgs() << ".. gave up (wrong calling convention)\n");
+    return false;
+  }
+
+  static const MCPhysReg GPR32ArgRegs[] = {Mips::A0, Mips::A1, Mips::A2,
+                                           Mips::A3};
+  static const MCPhysReg FGR32ArgRegs[] = {Mips::F12, Mips::F14};
+  static const MCPhysReg AFGR64ArgRegs[] = {Mips::D6, Mips::D7};
+
+  struct AllocatedReg {
+    const TargetRegisterClass *RC;
+    unsigned Reg;
+    AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
+        : RC(RC), Reg(Reg) {}
+  };
+
+  // Only handle simple cases. i.e. Up to four integer arguments.
+  // Supporting floating point significantly complicates things so we leave
+  // that out for now.
+  SmallVector<AllocatedReg, 4> Allocation;
+  unsigned Idx = 1;
+  bool HasAllocatedNonFGR = false;
+  for (const auto &FormalArg : F->args()) {
+    if (Idx > 4) {
+      DEBUG(dbgs() << ".. gave up (too many arguments)\n");
+      return false;
+    }
+
+    if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
+        F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
+        F->getAttributes().hasAttribute(Idx, Attribute::ByVal)) {
+      DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
+      return false;
+    }
+
+    Type *ArgTy = FormalArg.getType();
+    if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
+      DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
+      return false;
+    }
+
+    EVT ArgVT = TLI.getValueType(DL, ArgTy);
+    DEBUG(dbgs() << ".. " << (Idx - 1) << ": " << ArgVT.getEVTString() << "\n");
+    if (!ArgVT.isSimple()) {
+      DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
+      return false;
+    }
+
+    switch (ArgVT.getSimpleVT().SimpleTy) {
+    case MVT::i1:
+    case MVT::i8:
+    case MVT::i16:
+      if (!F->getAttributes().hasAttribute(Idx, Attribute::SExt) &&
+          !F->getAttributes().hasAttribute(Idx, Attribute::ZExt)) {
+        // It must be any extend, this shouldn't happen for clang-generated IR
+        // so just fall back on SelectionDAG.
+        DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
+        return false;
+      }
+      DEBUG(dbgs() << ".. .. GPR32(" << GPR32ArgRegs[Idx - 1] << ")\n");
+      Allocation.emplace_back(&Mips::GPR32RegClass, GPR32ArgRegs[Idx - 1]);
+      HasAllocatedNonFGR = true;
+      break;
+
+    case MVT::i32:
+      if (F->getAttributes().hasAttribute(Idx, Attribute::ZExt)) {
+        // The O32 ABI does not permit a zero-extended i32.
+        DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
+        return false;
+      }
+      DEBUG(dbgs() << ".. .. GPR32(" << GPR32ArgRegs[Idx - 1] << ")\n");
+      Allocation.emplace_back(&Mips::GPR32RegClass, GPR32ArgRegs[Idx - 1]);
+      HasAllocatedNonFGR = true;
+      break;
+
+    case MVT::f32:
+      if (Idx > 2 || HasAllocatedNonFGR) {
+        DEBUG(dbgs() << ".. .. gave up (f32 arg needed i32)\n");
+        return false;
+      } else {
+        DEBUG(dbgs() << ".. .. FGR32(" << FGR32ArgRegs[Idx - 1] << ")\n");
+        Allocation.emplace_back(&Mips::FGR32RegClass, FGR32ArgRegs[Idx - 1]);
+      }
+      break;
+
+    case MVT::f64:
+      if (Idx > 2 || HasAllocatedNonFGR) {
+        DEBUG(dbgs() << ".. .. gave up (f64 arg needed 2xi32)\n");
+        return false;
+      } else {
+        DEBUG(dbgs() << ".. .. AFGR64(" << AFGR64ArgRegs[Idx - 1] << ")\n");
+        Allocation.emplace_back(&Mips::AFGR64RegClass, AFGR64ArgRegs[Idx - 1]);
+      }
+      break;
+
+    default:
+      DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
+      return false;
+    }
+
+    ++Idx;
+  }
+
+  Idx = 0;
+  for (const auto &FormalArg : F->args()) {
+    unsigned SrcReg = Allocation[Idx].Reg;
+    unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[Idx].RC);
+    // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
+    // Without this, EmitLiveInCopies may eliminate the livein if its only
+    // use is a bitcast (which isn't turned into an instruction).
+    unsigned ResultReg = createResultReg(Allocation[Idx].RC);
+    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+            TII.get(TargetOpcode::COPY), ResultReg)
+        .addReg(DstReg, getKillRegState(true));
+    updateValueMap(&FormalArg, ResultReg);
+    ++Idx;
+  }
+
+  return true;
+}
+
 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
   if (!TargetSupported)
     return false;
 
   CallingConv::ID CC = CLI.CallConv;
   bool IsTailCall = CLI.IsTailCall;
   bool IsVarArg = CLI.IsVarArg;
   const Value *Callee = CLI.Callee;

test/CodeGen/Mips/Fast-ISel/br1.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @b = global i32 1, align 4
 @i = global i32 0, align 4
 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
 
 ; Function Attrs: nounwind
 define void @br() #0 {

test/CodeGen/Mips/Fast-ISel/bswap1.ll

 ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
-; RUN:      -fast-isel-abort=1 | FileCheck %s \
+; RUN:      -fast-isel-abort=3 | FileCheck %s \
 ; RUN:      -check-prefix=ALL -check-prefix=32R1
 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
-; RUN:      -fast-isel-abort=1 | FileCheck %s \
+; RUN:      -fast-isel-abort=3 | FileCheck %s \
 ; RUN:      -check-prefix=ALL -check-prefix=32R2
 
 @a = global i16 -21829, align 2
 @b = global i32 -1430532899, align 4
 @a1 = common global i16 0, align 2
 @b1 = common global i32 0, align 4
 
 declare i16 @llvm.bswap.i16(i16)

test/CodeGen/Mips/Fast-ISel/callabi.ll

 ; RUN: llc -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
-; RUN:     -fast-isel-abort=1 -verify-machineinstrs < %s | \
+; RUN:     -fast-isel-abort=3 -verify-machineinstrs < %s | \
 ; RUN:     FileCheck %s -check-prefixes=ALL,32R1
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
-; RUN:     -fast-isel-abort=1 -verify-machineinstrs < %s | \
+; RUN:     -fast-isel-abort=3 -verify-machineinstrs < %s | \
 ; RUN:     FileCheck %s -check-prefixes=ALL,32R2
 
 declare void @xb(i8)
 
 define void @cxb() {
   ; ALL-LABEL:    cxb:
 
   ; ALL:            addiu   $[[T0:[0-9]+]], $zero, 10
define void @cxcccc() {
   ; 32R1-DAG:       sra     $5, $[[T6]], 24
   ; 32R1-DAG:       sll     $[[T7:[0-9]+]], $[[T2]], 24
   ; 32R1-DAG:       sra     $6, $[[T7]], 24
   ; 32R1:           lw      $[[T8:[0-9]+]], 16($sp)
   ; 32R1:           sll     $[[T9:[0-9]+]], $[[T8]], 24
   ; 32R1:           sra     $7, $[[T9]], 24
 
   ; 32R2-DAG:       seb     $[[T4:[0-9]+]], $[[T0]]
   ; 32R2-DAG:       sw      $4, 16($sp)
   ; 32R2-DAG:       move    $4, $[[T4]]
   ; 32R2-DAG:       seb     $5, $[[T1]]
   ; 32R2-DAG:       seb     $6, $[[T2]]
   ; 32R2-DAG:       lw      $[[T5:[0-9]+]], 16($sp)
   ; 32R2:           seb     $7, $[[T5]]
   call void @xcccc(i8 88, i8 44, i8 11, i8 33)
   ret void
 }
 
 declare void @xhhhh(i16, i16, i16, i16)
 
 define void @cxhhhh() {
define void @cxhhhh() {
   ; 32R1-DAG:       sra     $5, $[[T6]], 16
   ; 32R1-DAG:       sll     $[[T7:[0-9]+]], $[[T2]], 16
   ; 32R1-DAG:       sra     $6, $[[T7]], 16
   ; 32R1:           lw      $[[T8:[0-9]+]], 16($sp)
   ; 32R1:           sll     $[[T9:[0-9]+]], $[[T8]], 16
   ; 32R1:           sra     $7, $[[T9]], 16
 
   ; 32R2-DAG:       seh     $[[T4:[0-9]+]], $[[T0]]
   ; 32R2-DAG:       sw      $4, 16($sp)
   ; 32R2-DAG:       move    $4, $[[T4]]
   ; 32R2-DAG:       seh     $5, $[[T1]]
   ; 32R2-DAG:       seh     $6, $[[T2]]
   ; 32R2-DAG:       lw      $[[T5:[0-9]+]], 16($sp)
   ; 32R2:           seh     $7, $[[T5]]
   call void @xhhhh(i16 88, i16 44, i16 11, i16 33)
   ret void
 }
 
 declare void @xiiii(i32, i32, i32, i32)
 
 define void @cxiiii() {

test/CodeGen/Mips/Fast-ISel/constexpr-address.ll

 ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \
-; RUN:     -fast-isel=true -fast-isel-abort=1 < %s | FileCheck %s
+; RUN:     -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \
-; RUN:     -fast-isel=true -fast-isel-abort=1 < %s | FileCheck %s
+; RUN:     -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s
 
 @ARR = external global [10 x i32], align 4
 
 define void @foo() {
 ; CHECK-LABEL: foo
 
 ; CHECK-DAG:    lw      $[[ARR:[0-9]+]], %got(ARR)({{.*}})
 ; CHECK-DAG:    addiu   $[[T0:[0-9]+]], $zero, 12345
 ; CHECK:        sw      $[[T0]], 8($[[ARR]])
 
 entry:
   store i32 12345, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @ARR, i32 0, i32 2), align 4
   ret void
 }

test/CodeGen/Mips/Fast-ISel/div1.ll

 ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
-; RUN:      -fast-isel-abort=1 | FileCheck %s
+; RUN:      -fast-isel-abort=3 | FileCheck %s
 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
-; RUN:      -fast-isel-abort=1 | FileCheck %s
+; RUN:      -fast-isel-abort=3 | FileCheck %s
 
 @sj = global i32 200000, align 4
 @sk = global i32 -47, align 4
 @uj = global i32 200000, align 4
 @uk = global i32 43, align 4
 @si = common global i32 0, align 4
 @ui = common global i32 0, align 4
 

test/CodeGen/Mips/Fast-ISel/fastalloca.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s -verify-machineinstrs | FileCheck %s
 
 %struct.x = type { i32 }
 
 @i = common global i32 0, align 4
 
 define i32 @foobar(i32 signext %x) {
 entry:

test/CodeGen/Mips/Fast-ISel/fpcmpa.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     -verify-machineinstrs < %s | FileCheck %s
 
 @f1 = common global float 0.000000e+00, align 4
 @f2 = common global float 0.000000e+00, align 4
 @b1 = common global i32 0, align 4
 @d1 = common global double 0.000000e+00, align 8
 @d2 = common global double 0.000000e+00, align 8
 

test/CodeGen/Mips/Fast-ISel/fpext.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @f = global float 0x40147E6B80000000, align 4
 @d_f = common global double 0.000000e+00, align 8
 @.str = private unnamed_addr constant [6 x i8] c"%f  \0A\00", align 1
 
 ; Function Attrs: nounwind
 define void @dv() #0 {

test/CodeGen/Mips/Fast-ISel/fpintconv.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 
 @f = global float 0x40D6E83280000000, align 4
 @d = global double 0x4132D68780000000, align 8
 @i_f = common global i32 0, align 4
 @i_d = common global i32 0, align 4
 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1

test/CodeGen/Mips/Fast-ISel/fptrunc.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @d = global double 0x40147E6B74DF0446, align 8
 @f = common global float 0.000000e+00, align 4
 @.str = private unnamed_addr constant [6 x i8] c"%f  \0A\00", align 1
 
 ; Function Attrs: nounwind
 define void @fv() #0 {

test/CodeGen/Mips/Fast-ISel/icmpa.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @c = global i32 4, align 4
 @d = global i32 9, align 4
 @uc = global i32 4, align 4
 @ud = global i32 9, align 4
 @b1 = common global i32 0, align 4
 

test/CodeGen/Mips/Fast-ISel/loadstore2.ll

 ; ModuleID = 'loadstore2.c'
 target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
 target triple = "mips--linux-gnu"
 
 @c2 = common global i8 0, align 1
 @c1 = common global i8 0, align 1
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @s2 = common global i16 0, align 2
 @s1 = common global i16 0, align 2
 @i2 = common global i32 0, align 4
 @i1 = common global i32 0, align 4
 @f2 = common global float 0.000000e+00, align 4
 @f1 = common global float 0.000000e+00, align 4

test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s -check-prefix=mips32r2
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s -check-prefix=mips32
 
 @b2 = global i8 0, align 1
 @b1 = global i8 1, align 1
 @uc1 = global i8 0, align 1
 @uc2 = global i8 -1, align 1
 @sc1 = global i8 -128, align 1
 @sc2 = global i8 127, align 1

test/CodeGen/Mips/Fast-ISel/loadstrconst.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
 @s = common global i8* null, align 4
 
 ; Function Attrs: nounwind
 define void @foo() #0 {
 entry:

test/CodeGen/Mips/Fast-ISel/logopm.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s
 
 @ub1 = common global i8 0, align 1
 @ub2 = common global i8 0, align 1
 @ub3 = common global i8 0, align 1
 @uc1 = common global i8 0, align 1
 @uc2 = common global i8 0, align 1
 @uc3 = common global i8 0, align 1
 @us1 = common global i16 0, align 2

test/CodeGen/Mips/Fast-ISel/memtest1.ll

 ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
-; RUN:     -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \
+; RUN:     -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \
 ; RUN:     -check-prefix=ALL -check-prefix=32R1
 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
-; RUN:     -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \
+; RUN:     -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \
 ; RUN:     -check-prefix=ALL -check-prefix=32R2
 
 @str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1
 @src = global i8* getelementptr inbounds ([12 x i8], [12 x i8]* @str, i32 0, i32 0), align 4
 @i = global i32 12, align 4
 @dest = common global [50 x i8] zeroinitializer, align 1
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1)

test/CodeGen/Mips/Fast-ISel/nullvoid.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 ; Function Attrs: nounwind
 define void @foo() {
 entry:
   ret void
 ; CHECK: jr $ra
 }

test/CodeGen/Mips/Fast-ISel/overflt.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @x = common global [128000 x float] zeroinitializer, align 4
 @y = global float* getelementptr inbounds ([128000 x float], [128000 x float]* @x, i32 0, i32 0), align 4
 @result = common global float 0.000000e+00, align 4
 @.str = private unnamed_addr constant [5 x i8] c"%f \0A\00", align 1
 
 ; Function Attrs: nounwind

test/CodeGen/Mips/Fast-ISel/rem1.ll

 ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
-; RUN:      -fast-isel-abort=1 | FileCheck %s
+; RUN:      -fast-isel-abort=3 | FileCheck %s
 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
-; RUN:      -fast-isel-abort=1 | FileCheck %s
+; RUN:      -fast-isel-abort=3 | FileCheck %s
 
 @sj = global i32 200, align 4
 @sk = global i32 -47, align 4
 @uj = global i32 200, align 4
 @uk = global i32 43, align 4
 @si = common global i32 0, align 4
 @ui = common global i32 0, align 4
 

test/CodeGen/Mips/Fast-ISel/retabi.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
 
 @i = global i32 75, align 4
 @s = global i16 -345, align 2
 @c = global i8 118, align 1
 @f = global float 0x40BE623360000000, align 4
 @d = global double 1.298330e+03, align 8
 

test/CodeGen/Mips/Fast-ISel/shftopm.ll

 ; RUN: llc -march=mipsel -relocation-model=pic -O0 \
-; RUN:     -fast-isel-abort=1 -mcpu=mips32r2  < %s | FileCheck %s
+; RUN:     -fast-isel-abort=3 -mcpu=mips32r2  < %s | FileCheck %s
 ; RUN: llc -march=mipsel -relocation-model=pic -O0 \
-; RUN:     -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s
+; RUN:     -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s
 
 @s1 = global i16 -89, align 2
 @s2 = global i16 4, align 2
 @us1 = global i16 -503, align 2
 @us2 = global i16 5, align 2
 @s3 = common global i16 0, align 2
 @us3 = common global i16 0, align 2
 

test/CodeGen/Mips/Fast-ISel/simplestore.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @abcd = external global i32
 
 ; Function Attrs: nounwind
 define void @foo()  {
 entry:
   store i32 12345, i32* @abcd, align 4
 ; CHECK:  addiu $[[REG1:[0-9]+]], $zero, 12345
 ; CHECK:  lw  $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}})
 ; CHECK:  sw  $[[REG1]], 0($[[REG2]])
   ret void
 }
 

test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s 
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s -check-prefix=mips32r2 
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s -check-prefix=mips32
 
 @f = common global float 0.000000e+00, align 4
 @de = common global double 0.000000e+00, align 8
 
 ; Function Attrs: nounwind
 define void @f1() #0 {
 entry:

test/CodeGen/Mips/Fast-ISel/simplestorei.ll

-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
-; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \
 ; RUN:     < %s | FileCheck %s
 
 @ijk = external global i32
 
 ; Function Attrs: nounwind
 define void @si2_1() #0 {
 entry:
   store i32 32767, i32* @ijk, align 4