[CodeGen] Refactor MachineMemOperand::Flags's target-specific flags.

[jlebar]

Summary

Make the target-specific flags in MachineMemOperand::Flags real, bona
fide enum values. This simplifies users, prevents various constants
from going out of sync, and avoids the false sense of security provided
by declaring static members in classes and then forgetting to define
them inside of cpp files.

[MatzeB]

LGTM

include/llvm/CodeGen/MachineMemOperand.h

 /// Instead of holding a StoreInst or LoadInst, this class holds the address
 /// Value of the reference along with a byte size and offset. This allows it
 /// to describe lowered loads and stores. Also, the special PseudoSourceValue
 /// objects can be used to represent loads and stores to memory locations
 /// that aren't explicit in the regular LLVM IR.
 ///
 class MachineMemOperand {
 public:
-  // This is the number of bits we need to represent flags.
-  static LLVM_CONSTEXPR unsigned MOMaxBits = 8;
-
-  // Target hints allow target passes to annotate memory operations.
-  static LLVM_CONSTEXPR unsigned MOTargetStartBit = 5;
-  static LLVM_CONSTEXPR unsigned MOTargetNumBits = 3;
-
   /// Flags values. These may be or'd together.
   enum Flags : uint16_t {
     // No flags set.
     MONone = 0,
     /// The memory access reads data.
-    MOLoad = 1,
+    MOLoad = 1u << 0,
     /// The memory access writes data.
-    MOStore = 2,
+    MOStore = 1u << 1,
     /// The memory access is volatile.
-    MOVolatile = 4,
+    MOVolatile = 1u << 2,
     /// The memory access is non-temporal.
-    MONonTemporal = 8,
+    MONonTemporal = 1u << 3,
     /// The memory access is invariant.
-    MOInvariant = 16,
+    MOInvariant = 1u << 4,
 
-    // Maximum MemOperandFlag value (inclusive).
-    MOMaxFlag = (1 << MOMaxBits) - 1,
+    // Reserved for use by target-specific passes.
+    MOTargetFlag1 = 1u << 5,
+    MOTargetFlag2 = 1u << 6,
+    MOTargetFlag3 = 1u << 7,
 
-    LLVM_MARK_AS_BITMASK_ENUM(MOMaxFlag)
+    LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag3)
   };
 
 private:
   MachinePointerInfo PtrInfo;
   uint64_t Size;
   Flags FlagVals;
   uint16_t BaseAlignLog2; // log_2(base_alignment) + 1
   AAMDNodes AAInfo;

lib/CodeGen/MachineInstr.cpp

 }
 
 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
                                      uint64_t s, unsigned int a,
                                      const AAMDNodes &AAInfo,
                                      const MDNode *Ranges)
     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
       AAInfo(AAInfo), Ranges(Ranges) {
-  assert(MOMaxFlag == (1 << MOMaxBits) - 1 &&
-         "MOMaxFlag and MOMaxBits have fallen out of sync.");
   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
           isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
          "invalid pointer value");
   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
   assert((isLoad() || isStore()) && "Not a load/store!");
 }
 
 /// Profile - Gather unique data for the object.

lib/Target/AArch64/AArch64InstrInfo.h

 #include "AArch64GenInstrInfo.inc"
 
 namespace llvm {
 
 class AArch64Subtarget;
 class AArch64TargetMachine;
 
 class AArch64InstrInfo : public AArch64GenInstrInfo {
-  // Reserve bits in the MachineMemOperand target hint flags, starting at 1.
-  // They will be shifted into MOTargetHintStart when accessed.
-  enum TargetMemOperandFlags {
-    MOSuppressPair = 1
-  };
-
   const AArch64RegisterInfo RI;
   const AArch64Subtarget &Subtarget;
 
 public:
   explicit AArch64InstrInfo(const AArch64Subtarget &STI);
 
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should

lib/Target/AArch64/AArch64InstrInfo.cpp

 #include "llvm/Support/TargetRegistry.h"
 #include <algorithm>
 
 using namespace llvm;
 
 #define GET_INSTRINFO_CTOR_DTOR
 #include "AArch64GenInstrInfo.inc"
 
+static constexpr MachineMemOperand::Flags MOSuppressPair =
+    MachineMemOperand::MOTargetFlag1;
+
 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
     : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
       RI(STI.getTargetTriple()), Subtarget(STI) {}
 
 /// GetInstSize - Return the number of bytes of code the specified
 /// instruction may be.  This returns the maximum number of bytes.
 unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
   const MachineBasicBlock &MBB = *MI.getParent();
case AArch64::STRXroX:
     AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val);
     return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val);
   }
   return false;
 }
 
 /// Check all MachineMemOperands for a hint to suppress pairing.
 bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) const {
-  static_assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits),
-                "Too many target MO flags");
-  for (auto *MM : MI.memoperands()) {
-    if (MM->getFlags() &
-        (MOSuppressPair << MachineMemOperand::MOTargetStartBit)) {
-      return true;
-    }
-  }
-  return false;
+  return any_of(MI.memoperands(), [](MachineMemOperand *MMO) {
+    return MMO->getFlags() & MOSuppressPair;
+  });
 }
 
 /// Set a flag on the first MachineMemOperand to suppress pairing.
 void AArch64InstrInfo::suppressLdStPair(MachineInstr &MI) const {
   if (MI.memoperands_empty())
     return;
-
-  static_assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits),
-                "Too many target MO flags");
-  (*MI.memoperands_begin())
-      ->setFlags(static_cast<MachineMemOperand::Flags>(
-          MOSuppressPair << MachineMemOperand::MOTargetStartBit));
+  (*MI.memoperands_begin())->setFlags(MOSuppressPair);
 }
 
 bool AArch64InstrInfo::isUnscaledLdSt(unsigned Opc) const {
   switch (Opc) {
   default:
     return false;
   case AArch64::STURSi:
   case AArch64::STURDi: