[X86] Add costs for SSE zext/sext to v4i64 to TTI

[mkuper]

Summary

The costs are somewhat hand-wavy, but should be much closer to the truth - what we get from the target-independent code right now is ridiculously high.

The underlying problem seems to be that the target-independent code in BasicTTIImpl assumes that if the dest type is illegal, the operation will get completely scalarized. This is, of course, nonsense. What it should probably do is take the legalization cost + 2 * the actual cost of the extend after the split (by querying the concrete TTI on the result vector).
This problem isn't unique to casts, there's similar logic for, at least, arithmetic instructions and selects. Changing that right now seems like it would rock the boat too much, I want to see if I run into more cases like this in practice first.

[RKSimon]

Why isn't the legalization/cost scale values from getTypeLegalizationCost not working?

[mkuper]

Because BasicTTIImpl::getCastInstrCost() doesn't even try to use it for vector sexts/zexts. It just assumes scalarization.

This is the case we fall into:

// If we are converting vectors and the operation is illegal, or
// if the vectors are legalized to different types, estimate the
// scalarization costs.
unsigned Num = Dst->getVectorNumElements();
unsigned Cost = static_cast<T *>(this)->getCastInstrCost(
    Opcode, Dst->getScalarType(), Src->getScalarType());

// Return the cost of multiple scalar invocation plus the cost of
// inserting and extracting the values.
return getScalarizationOverhead(Dst, true, true) + Num * Cost;

Changing this (and the other two places where we have the same logic) to use getTypeLegalizationCost() and query getCastInstrCost() for the legalized type was what I meant above.

[RKSimon]

Thanks I get that now - please can you either add a descriptive TODO comment or raise a BZ explaining why this isn't working.

Other than that, we already have plenty of costs that are in similar situations, so LGTM.

lib/Target/X86/X86TargetTransformInfo.cpp

static const TypeConversionCostTblEntry AVXConversionTbl[] = {
     // vector-extract, one scalar conversion and one vector-insert).  The
     // problem is that the inserts form a read-modify-write chain so latency
     // should be factored in too.  Inflating the cost per element by 1.
     { ISD::FP_TO_UINT,  MVT::v8i32, MVT::v8f32, 8*4 },
     { ISD::FP_TO_UINT,  MVT::v4i32, MVT::v4f64, 4*4 },
   };
 
   static const TypeConversionCostTblEntry SSE41ConversionTbl[] = {
+    { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32,   2 },
+    { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32,   2 },
+    { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16,   2 },
+    { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16,   2 },
+    { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8,    2 },
+    { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8,    2 },
+
     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 4 },
     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  2 },
     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  2 },
     { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i16,  1 },
     { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i16,  1 },
     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8,  4 },
     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8,  4 },
static const TypeConversionCostTblEntry SSE2ConversionTbl[] = {
     { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 8 },
     { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
     { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
     { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
 
+    { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32,   3 },
+    { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32,   5 },
+    { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16,   3 },
+    { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16,  10 },
+    { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i8,    4 },
+    { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8,    8 },
+
     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 6 },
     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 8 },
     { ISD::ZERO_EXTEND, MVT::v8i32,  MVT::v8i16,  3 },
     { ISD::SIGN_EXTEND, MVT::v8i32,  MVT::v8i16,  4 },
     { ISD::ZERO_EXTEND, MVT::v4i32,  MVT::v4i16,  1 },
     { ISD::SIGN_EXTEND, MVT::v4i32,  MVT::v4i16,  2 },
     { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8,  9 },
     { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8,  12 },

test/Analysis/CostModel/X86/sse-itoi.ll

 ; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+sse2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s
 ; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+sse4.1 -cost-model -analyze < %s | FileCheck --check-prefix=SSE41 %s
 
+define void @zext_v4i8_to_v4i64(<4 x i8>* %a) {
+; SSE2: zext_v4i8_to_v4i64
+; SSE2: cost of 4 {{.*}} zext
+;
+; SSE41: zext_v4i8_to_v4i64
+; SSE41: cost of 2 {{.*}} zext
+;
+  %1 = load <4 x i8>, <4 x i8>* %a
+  %2 = zext <4 x i8> %1 to <4 x i64>
+  store <4 x i64> %2, <4 x i64>* undef, align 4
+  ret void
+}
+
+define void @sext_v4i8_to_v4i64(<4 x i8>* %a) {
+; SSE2: sext_v4i8_to_v4i64
+; SSE2: cost of 8 {{.*}} sext
+;
+; SSE41: sext_v4i8_to_v4i64
+; SSE41: cost of 2 {{.*}} sext
+;
+  %1 = load <4 x i8>, <4 x i8>* %a
+  %2 = sext <4 x i8> %1 to <4 x i64>
+  store <4 x i64> %2, <4 x i64>* undef, align 4
+  ret void
+}
+
+define void @zext_v4i16_to_v4i64(<4 x i16>* %a) {
+; SSE2: zext_v4i16_to_v4i64
+; SSE2: cost of 3 {{.*}} zext
+;
+; SSE41: zext_v4i16_to_v4i64
+; SSE41: cost of 2 {{.*}} zext
+;
+  %1 = load <4 x i16>, <4 x i16>* %a
+  %2 = zext <4 x i16> %1 to <4 x i64>
+  store <4 x i64> %2, <4 x i64>* undef, align 4
+  ret void
+}
+
+define void @sext_v4i16_to_v4i64(<4 x i16>* %a) {
+; SSE2: sext_v4i16_to_v4i64
+; SSE2: cost of 10 {{.*}} sext
+;
+; SSE41: sext_v4i16_to_v4i64
+; SSE41: cost of 2 {{.*}} sext
+;
+  %1 = load <4 x i16>, <4 x i16>* %a
+  %2 = sext <4 x i16> %1 to <4 x i64>
+  store <4 x i64> %2, <4 x i64>* undef, align 4
+  ret void
+}
+
+
+define void @zext_v4i32_to_v4i64(<4 x i32>* %a) {
+; SSE2: zext_v4i32_to_v4i64
+; SSE2: cost of 3 {{.*}} zext
+;
+; SSE41: zext_v4i32_to_v4i64
+; SSE41: cost of 2 {{.*}} zext
+;
+  %1 = load <4 x i32>, <4 x i32>* %a
+  %2 = zext <4 x i32> %1 to <4 x i64>
+  store <4 x i64> %2, <4 x i64>* undef, align 4
+  ret void
+}
+
+define void @sext_v4i32_to_v4i64(<4 x i32>* %a) {
+; SSE2: sext_v4i32_to_v4i64
+; SSE2: cost of 5 {{.*}} sext
+;
+; SSE41: sext_v4i32_to_v4i64
+; SSE41: cost of 2 {{.*}} sext
+;
+  %1 = load <4 x i32>, <4 x i32>* %a
+  %2 = sext <4 x i32> %1 to <4 x i64>
+  store <4 x i64> %2, <4 x i64>* undef, align 4
+  ret void
+}
+
 define void @zext_v16i16_to_v16i32(<16 x i16>* %a) {
 ; SSE2: zext_v16i16_to_v16i32
 ; SSE2: cost of 6 {{.*}} zext
 ;
 ; SSE41: zext_v16i16_to_v16i32
 ; SSE41: cost of 4 {{.*}} zext
 ;
   %1 = load <16 x i16>, <16 x i16>* %a